I've been looking a bit at the news recently about the intel 12th gen CPUs, and how they disable the AVX-512 instruction set if the efficiency cores are enabled. which seemed like a weird and poor implementation that bottlenecks some workloads and leaves quite a bit on the table in terms of performance. Why isn't this handled in the scheduler ? all the major operating systems already support the big/small core design. Why isn't the instruction set requirements simply passed to the scheduler via program headers to dynamically schedule tasks in the most efficient/fastest manner?
I read a bit up on the topics and there is already research into the topics. so I wonder why the approach intel used is even there. http://web.cs.ucla.edu/~tjn/papers/pact2018-hybrid-sched.pdf
Why isn't a better solution used? and why just disable the functionally as it seems like low hanging performance gains from intels side? And isn't this a approach to also look into more as modern hardware utilize ASIC style or dedicated hardware for more operations and will so going forward?
