I read a bit up on the topics and there is already research into the topics. so I wonder why the approach intel used is even there. http://web.cs.ucla.edu/~tjn/papers/pact2018-hybrid-sched.pdf
Why isn't a better solution used? and why just disable the functionally as it seems like low hanging performance gains from intels side? And isn't this a approach to also look into more as modern hardware utilize ASIC style or dedicated hardware for more operations and will so going forward?