I was hoping that the next iteration would start using USB-C even if it costed a bit more per-board.
https://www.raspberrypi.com/for-industry/powered-by/product-...
Thought it might be the cable at first, but it was general. Just couldn’t think of a reason why it wasn’t supported though…
1: I still have a ton of micro-USB cables, and a decreasing number of things to use them for. Some are unused, still in unopened packages.
2: Devices like this don't get moved and plugged/unplugged frequently, which is what kills the connector.
> Picossci2 Breakout is a drop-in replacement for Pico 2, with a USB-C connector.
My guess is the RPi foundation has a _ton_ of extra micro USB connectors they want to use up.
In the past, when usb-c just got introduced micro usb ports for significantly cheaper than usb-c, so it made some sense. Today, it makes no sense.
The amount of different variations of Raspberry Pi's I've been collecting over the years for no good reason, all doing nothing. And I don't even consider myself part of the upper echelon/extremists when it comes to this.
With that said, I wonder when we will get Raspberry Pi Pico 2 W (with wireless/Bluetooth capabilites)
> The unique dual-core, dual-architecture capability of RP2350 provides a pair of industry-standard Arm Cortex-M33 cores, and a pair of open-hardware Hazard3 RISC-V cores, selectable in software or by programming the on-chip OTP memory.
Kind of interesting... Two architectures in one chip? https://www.raspberrypi.com/products/rp2350/
Datasheets say they’re 21x51mm. Looks like they’re on the order of 5mm deep. So 5.35mL per Pico.
Four million of these would be 5659 gallons of Picos, 756 cubic feet.
So you could take the e-waste of every Pico sold to date, and put it in a single 9.1ft cube in your garage.
I’d argue that this doesn’t qualify as something we shouldn’t spend time worrying about. There’s probably at least one Pico, maybe running a sign at some EPA office, doing more good for the environment than all the waste from all of them together is causing harm.
Literally everyone in the developed world is guilty of being irresponsible with digital waste/footprint.
If you already have any kids at all (for example), there's nothing you can do to reduce your damage to the earth. Go ahead and as many raspberry pis as will fit in your junk drawer and don't give it a second thought.
If you ever get on a plane for vacation, same story. Raspberry Pi is a rounding error.
If you buy a new phone every few years, again same story.
This is a misanthropic perspective, we should have no kids and die out to reduce ‘damage to the earth’. Best environmentalist is a mass murderer. Worst climate criminal is a sperm donor.
But if you look at the physical world, Earth already had 6 mass extinction events, asteroids, supervolcanoes, etc. they killed basically everything, and life bounces back. There will be more. Our efforts are unimpressive in comparison. In absolute, it doesn’t matter.
From a humanist view, ‘Damage to the earth’ is damage to its ability to support human life. That’s the perspective that makes sense to me.
One of the requirements is that civilisation continues.
And the best contribution is to bring up a well adjusted, kind and capable individual, and for them to do the same.
If lump together environmental impact of children and parents, then if your bloodline continues forever your evrironmental impact is infinite. This creative accounting leads to absurd conclusions
Did you consider used market? I was stupid enough to not take the opportunity to make some good money when even ancient ones were unobtanium and overpriced everywhere, but recently managed to sell all my older ones at a decent price, so no direct waste was produced.
What concerns me more about this Pico however is the signed boot locking feature that if not reversible could lock a Pico to the original program forever, so an used one couldn't be repurposed for anything else even if a non malicious user wanted to reflash it entirely without reading the original content. I'm not sure about that so I'd welcome more information on the subject: could signed boot locking be reversed with a complete flash erase?
There are bigger things that produce way more waste though. Lots of vehicles (especially boats) have huge fiberglass composite components for example.
Raspberry Pi Foundation released a RP2040 based dev board(Pico W) with an additional external wireless chip, as have others(including boards with an additional ESP32 just do comms).
>Before the end of the year, we expect to ship a wireless-enabled Pico 2 W, using the same Infineon 43439 modem as Pico W, and versions of both Pico 2 and Pico 2 W with pre-installed 0.1-inch headers.
(And, like the predecessor Pi Pico, a version with wireless will be coming later.)
That would be everything I need to develop web applications. I wonder if I could use a 3-piece setup to do so:
A keyboard connected to the Pi
The Pi connected to a tablet which acts as a monitor
[1]: https://chicagodist.com/products/raspberry-pi-4-model-b-1gb
I have built a few prototypes with Raspberry Pi Zeros, which are luxurious web servers -- 512mb of ram, capable of utilizing a 2tb sd card.
https://www.reddit.com/r/cyberDeck/
https://www.reddit.com/r/cyberDeck/comments/1eksn4a/3d_print...
Supposedly it didn’t require any measurable amount of additional die space, because other things constrained the minimum size of the die (like the I/O pads), according to one of the Raspberry Pi engineers.
An additional ARM core would have required significant changes to the crossbar. Right now, only two cores can be active, not three.
I think this type of pseudo-wasteful design is not unheard of when manufacturer had two markets to deliver to that had substantially different processing, but not I/O, requirements, as well as when some of major features in already manufactured chip didn't work out and ways to offset losses would be nice.
ISTR that some of their ESP32 boards do, though. i.e., charge LiPo through the USB port.
Also, I think some of the Heltec boards do. I have one here with a JST battery connector, but I haven't used it in so long, I'm not sure. I think this is the one I have: https://heltec.org/project/wifi-kit32-v3/
Though I'll also not I'm having some problems getting it to take an upload properly, but I tend to find most of the LILYGO stuff takes a little experimentation to get everything right, then it is reliable once you know what it likes.
I found some modules on aliexpress with usbc connector, for example:
- IP2326 https://www.aliexpress.com/item/1005007175222069.html
- CN3302 https://www.aliexpress.com/item/1005006203228418.html
but I haven't tested them yet.
You can also get version to fit the Pico, or even a RP2040 based board with integrated battery management.
Larger package (60 or 80 pins)
Variant with 2 MB in-package Flash
Secure boot and encrypted boot
Two security execution contexts
Random number generator
SHA-256 accelerator
8 kB of OTP ROM (separate from the 32 kB BOOTROM)
8 channel HSTX high speed serial transmitter
30->48 GPIO (18 more, in the 80 pins)
8->12 PIO state machines
12->16 DMA channels
RISC-V and ARM (selectable at boot, individually per core)
Cortex-M0+->Cortex-M33 (I don't know what that means in practice)
133->150 MHz core clock
https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.p...
Not in terms of the product specs (which are also really nice), but in terms of layout and content.
Indeed, that is a well-written technical book that one could read cover-to-cover. It has a clear progression of topics, and all of the text is beautifully written:
"Once secure boot is enabled, the bootrom verifies signatures of images from all supported media: flash, OTP, and images preloaded into SRAM via the UART and USB bootloaders. At this point you lose the ability to run unsigned images; during development you may find it more convenient to leave secure boot disabled. The next section describes the generation of signed images to run on a secure-boot-enabled device."
"The chip-level reset subsystem shares a register address space with other power management subsystems in the always-on domain. The address space is referred to as POWMAN elsewhere in this document. A complete list of POWMAN registers is provided in Section 6.4, “Power Management (POWMAN) Registers”, but information on registers associated with the brownout detector are repeated here."
"The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock sources, allowing the user to trade off performance against cost, board area and power consumption. From these sources it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies."
I am thoroughly impressed!!
I think the 60 pin version is the same size as RP2040.
Espressif apparently has their own WiFi implementation, which makes sense as they are a major vendor of very cheap tablet and cell phone WiFi radios. This is likely why they can offer that feature so cheaply.
Bluetooth Low Energy is way simpler BTW.
Data sheet [0] section "5.4 Powerchain" shows an external RT6150 buck-boost switcher with an external inductor.
0: https://datasheets.raspberrypi.com/pico/pico-2-datasheet.pdf
Edit: reading further in that section of the data sheet, "The RP2350 has an on-chip switching regulator that powers the digital core at 1.1V (nominal) from the 3.3V supply, which is not shown in Figure 7."
It has proven difficult enough to find a PDF of the schematic (I don't have Cadence Allegro installed) that I am giving up.
>RP2350 includes a pair of open-hardware Hazard3 RISC-V cores which can be substituted at boot time for the Cortex-M33 cores. Our boot ROM can even auto-detect the architecture for which a second-stage binary has been built and reboot the chip into the appropriate mode
https://www.raspberrypi.com/documentation/microcontrollers/s...
We’ve seen some amazing demonstrations of that power: from our very own Graham Sanderson’s port of DOOMThe post claims PSRAM is supported.
Either way, that seems like great news.
Datasheet section 12.4.1 "Changes from RP2040"
- Removed spikes in differential nonlinearity at codes 0x200, 0x600, 0xa00 and 0xe00, as documented by erratum RP2040-E11, improving the ADC’s precision by around 0.5 ENOB.
- Increased the number of external ADC input channels from 4 to 8 channels, in the QFN-80 package only.
https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.p...
> I can't compare the sizes of the two cores. The final die size would likely have been exactly the same with the Hazard3 removed, as std cell logic is compressible, and there is some rounding on the die dimensions due to constraints on the pad ring design. I can say that we taped out at a very high std cell utilisation and we might have saved a few grey hairs during final layout and STA by deleting the RISC-V cores.
> The maximum frequency for the HSTX clock is 150 MHz, the same as the system clock. With DDR output operation, this is a maximum data rate of 300 Mb/s per pin.
The investment was made nine months ago. Is a hardware design locked in at this point? We will see what happens in the future and whether we will get more RISC-V cores.