If one naively considers going from transistors of area a² on dies of area b² to transistors of volume a³ in a three dimensional die of volume b³, one finds that we could have quadrillions of transistors in a cube with side lengths of tens of millimetres using currently available transistor sizes. It would of course instantly melt itself due to the different scaling behaviors of different quantities.
But we can reduce transistor area only so much until we end up at the size of molecular or single atom transistors, we are currently probably on the order of hundred atoms side length.
But these are uses of the 3rd dimension within the transistor.
You are probably talking about a more global use of the 3rd dimension.
CFET technology is envisaged to exploit the 3rd dimension within logic cells. The idea is to stack the N-type transistors on top of the P-type transistors to save surface area.
But you are probably talking about an even more global use of the 3rd dimension. Where the idea would be something like stacking logic cells.
However, this will cause power supply and heat dissipation issues. Nowadays companies are trying to bring the power supply from the bottom of the transistor (so-called buried power rail) to leave more room on top for routing. If you start stacking logic gates, where should the power flows?
I supposed it’s a bit like elevators though. As you make the chip taller the real estate for transport goes up until the entire volume is dedicated to transportation.
It may be worth it for relatively low power uses like memory. And minimizing signal length.
In logic, people (Unity, for instance) talk about fully 3D, with stacks of transistors layered. This turns out to be capability and thermally limited.
The most interesting variant today are the N over P nanosheets. Instead of having N and P transistors next to each other, putting them on top saves area. Contact and interconnect are still limiting, but this gives a node shrink without lateral shrink.
It isn't completely obvious to me that this gives enough design flexibility to be worth it, but maybe?
So anyway, there are good attempts, and the stacked NPN is the most likely.
(Arrgh. They redesigned their already bad website into something even more bad)
There were some talks at semiconductor fabbing conferences with them, some presentations directly from them on youtube, some papers, some press(very little) over the past years.
I've seen no implementations, samples, not even prototypes so far. No design wins either. All theoretical. But seems plausible to me. So does vaporware.
At least they have an office address almost next to intel in Oregon :)
So for instance how much could you scale performance of a mobile chip by adding more transistors vertically until it has close to the same power draw as a desktop chip?
3D NAND (VNAND) is also fully vertical -- again, the logic is all on the wafer surface but the storage cells are built up.
It would be somewhat like 3D printing, you repeat a fundamentally two dimensional process along a third dimension over and over again. And to some extend this is exactly how chips are currently made, in many steps and layers to build up the different transistor parts and the interconnect.
But it could certainly be the case that this is not practical and one would have to look for fundamentally different processes to build up such structures, maybe some self-assembly process. But I really have no clue if and what has been considered, that is why I asked about it in the first place.
So of course let's not even mention any technology beyond silicon photolithography.
They mention a 1.5nm process node, which is 7.5 silicon atoms wide. So: A) why aren't we talking about 1.4 or 1.6 nm instead? And B) at what point will the industry acknowledge the need for atomically precise manufacturing?
Besides, using one metric to measure a 3D object wouldn’t make too much sense, at least in the case of a FinFET transistor. A more useful metric would be transistor density.
It seems I'm definitely in grumpy old man territory these days when things like the process node name which used to actually mean something specific, don't anymore.
Selective growth and patterning already have precision in the sub angstrom range, over mms of distance. This is what 'TMU' is, when you read an ASML or Lam paper on the topic. Current target is sub nm, for total variation cross die per layer.
I strongly recommend a read of the Tennant's law series onnlithoguru, or Tim Brunner's paper on why optical lithography wins forever.in short, optical is better (including EUV).
There are whole conferences dedicated to atomically precise manufactue, and hundreds of not thousands of people working in the field.
I think we are already there, some of the layers already have thicknesses of only five or so atoms.
[1] >//en.m.wikipedia.org/wiki/Fullerene
We're at the point where single-core performance gains on each generation are weak, and instead are now heading for massive parallelization. Is the the speed of light (more specifically, the speed of current) actually the limiting factor here?
At 5 Ghz, in the time it takes for the clock to tick once, light travels 6 cm (2.36 inches). I know electrical current moves even slower than that (and varies depending on the material), so is it possible that it could impact theoretical maximum performance per core, at least limiting clock speeds, due to signals going across the CPU and across components being out of sync?
