I supposed it’s a bit like elevators though. As you make the chip taller the real estate for transport goes up until the entire volume is dedicated to transportation.
In my post I didn't elaborate on thermal dissipation issues because I think there are already enough problems with geometry and routing.
But heat dissipation is already a concern today, even before increasing the number of transistor layers.
If in a modern chip all the transistors were active simultaneously at high frequency, then the chip would probably be destroyed instantly due to overheating.
This is called the "Power Wall", which limits the frequency and (active) transistor density.
In a modern circuit it is common for one part of the circuit not to be active simultaneously with an adjacent one in order to avoid overheating. It is also common to place blocks based on whether or not they are likely to be active at the same time. It's common to have logic only used for factory testing. (design for testability (DFT) and design for manufacturing (DFM)) It is also common to add logic cells connected to nothing which can be repurposed in case a bug is found in the hardware and we need to fix it without replacing all the manufacturing masks, which would cost millions of dollars. (which is called spare cell insertion)
All this constitutes what is called the darksilicon.
In the case of a 2D circuit, all the transistors are exposed to heat dissipation in approximately the same way. Now imagine the same problems, but in 3D, and adding the idea that some cells, in the center, can dissipate less heat than those near the surface. It must be a nightmare.
However, there is a potential solution to this problem: nanofluidics cooling.
There are materials that are electrical insulators but not thermal insulators, but I don't know how you put them into a chip. How long before we circle back to chips made of synthetic diamond?
Also as you stack the chip features deeper, does the variability in thermal expansion of all of the materials start to cause bigger and bigger problems? Is that an unspoken assumption under the umbrella of "moving heat from the middle of the chip"? I've seen midwestern roads after a hard winter and a hot summer. Thermal cycling can be brutal.
> The best design they found is able to handle heat fluxes up to 1,700 watts per square centimeter.
This was not a 3-dimensional chip, of course, but it might give a ballpark figure for the heat transfer we could achieve with nanofluidics. The article and paper authors take care to point out that this was effectively a "toy" example, with the circuit designed to be easy to cool.
