1Heliodor: An RVA23-Compliant Multicore Out-of-Order RISC-V Core in Veryl (opens in new tab)(veryl-lang.org)2dalance3d ago0Save
2Veryl Simulator: Performance Comparison with Verilator (opens in new tab)(veryl-lang.org)3dalance1mo ago0Save
3Veryl 0.20.0: logic synthesis and type inference are supported (opens in new tab)(veryl-lang.org)2dalance1mo ago0Save
4Veryl 0.16.4 – A Modern HDL as Alternative to SystemVerilog (opens in new tab)(veryl-lang.org)3dalance9mo ago0Save
5Veryl 0.16.0 – A Modern HDL as Alternative to SystemVerilog (opens in new tab)(veryl-lang.org)3dalance1y ago0Save
6Veryl 0.14.0 – A Modern HDL as Alternative to SystemVerilog (opens in new tab)(veryl-lang.org)2dalance1y ago0Save
8Verylup 0.1.2 – the official installer for Veryl (opens in new tab)(veryl-lang.org)1dalance1y ago0Save
9Veryl 0.13.0 – A Modern HDL as Alternative to SystemVerilog (opens in new tab)(veryl-lang.org)2dalance1y ago0Save
10Veryl 0.12.0 – A New Hardware Description Language (opens in new tab)(veryl-lang.org)1dalance1y ago0Save
11Veryl v0.12.0: A New Hardware Description Language (opens in new tab)(github.com)GitHub1dalance1y ago0Save
