[0] http://www.frank-buss.de/lispcpu/ [1] http://www.aviduratas.de/lisp/lispmfpga/
I will have a look when back at home.
There's significantly more for the TI Explorer Lisp machine: http://bitsavers.trailing-edge.com/pdf/ti/explorer/
And even more for Symbolics: http://bitsavers.trailing-edge.com/pdf/symbolics/
Xerox did a Lisp machine line: http://bitsavers.trailing-edge.com/pdf/xerox/interlisp/
There's a working emulator for the MIT CADR: http://www.unlambda.com/cadr/index.html
And you can of course run Genera in an emulator: http://www.unlambda.com/download/genera/
There's a semi working TI explorer emu: http://www.unlambda.com/lispm/
There's no indication of hardware support for garbage collection. It would probably be more useful to have tag bits to support GC than a LISP-oriented instruction set, especially if it allowed concurrent GC.
[1] http://www8.hp.com/hpnext/posts/discover-day-two-future-now-...
http://www.mail-archive.com/picolisp@software-lab.de/msg0483...
...But still no links to source. (As I understand it, this hardware design is expressed in the form of verilog source code.)
This is PilMCU, a hardware design which apparently runs PicoLisp.
Right now, only the design exists, not physical hardware. But you can run the design in a simulator. ...Something, something, verilog. (This is not my area of expertise.)
[Edit: the devs use the Icarus verilog compiler to provide simulations. It's available in Debian repositories.]
It seems they're interested in launching this is a commercial (or crowd-funded) hardware product.
For simulation, you compile verilog with a software tool into something executable by a VM or natively. This is heavily event based in execution, with events being edge transitions (a signal going from 0->1 or 1->0) occuring at specific times--for most (but not all) cases.
For producing something usable by an FPGA or a foundry for an ASIC, instead of compiling you synthesize. Different tool. Synthesis is the process of taking higher level hardware descriptions and outputing the lower level descriptions usually called a netlist. It's akin to translating C into assembly for example.
Device specific tools can take that netlist and create a bitstream for configuring an FPGA, or the foundry can take that netlist and go through a process called "physical synthesis" which takes the netlist and chooses from the foundry's library the components that will work best for that netlist to operate at speed, figure out where to place them on the die, and insert buffers as needed.
What the GP was asking: is this design small enough to fit in an FPGA. This question is orthogonal to the language used to describe the hardware.
I'd say they answer is yes, depending on the FPGA you choose. Some FPGAs are pretty high capacity these days, and even fast.
Enjoy (improvements and comments welcome).
