[0] https://cyber.nyu.edu/2024/07/22/chipchat-nyu-tandon-team-fa...
Looks like yes: https://store.efabless.com/products/tiny-tapeout-project
KenoFischer says no, Tiny Tapeout was using eFabless as their service provider and is looking into alternatives.
Something's fishy. https://efabless.com/news doesn't list any shutdown notices.
The IHP PDK is really a lot more exciting to me than the Skywater stuff because it's aimed at submillimeter analog things (450GHz fₜ, 650GHz fastest oscillator) and why would you fab a digital design in 130nm instead of just programming an FPGA?
That’s an interesting concept. So an fpga implemented on a current 7nm process is more performant (clock speed and energy use) than an asic on a 130nm process? How about 40nm process? I feel like there’s a graph of intersecting lines here.
Because you need some analog features with your digital design.
Far as 130nm, I'll give you a few reasons I'd use one over a 7nm FPGA. This is a non-HW guy saying what he's heard from pro's at different times. HW people, feel free to correct me about whatever I get wrong.
1. Unit prices. If you can take the upfront cost (NRE), the per unit price will be much lower than FPGA's. You might charge plenty per unit depending on the market. This can be a source of profit.
2. Older, larger nodes are said to be better for analog. Lots of designs are mixed-signal to use analog for it's lower power, extra performance, or how it doesn't blink (no rise/fall with clock).
3. ASIC's can't be reprogrammed like FPGA's. The custom design might be more secure like Sandia Secure Processor (Score) or CHERI RISC-V. FPGA's can only do one of these except for antifuse FPGA's.
4. Larger nodes are easier to visually inspect for backdoor with cheaper, teardown hardware. Who knows what's in the FPGA's.
5. Larger nodes are easier to synthesize, P&R, and auto-inspect (eg Calibre). That means open-source tools have a better chance of working or even being developed.
6. If not too power hungry (or power is cheap), some applications can let you outperform 7nm parts with parallel use of 130nm parts which are much cheaper or highly-optimized. An example what media wanting to do distributed, massively-parallel design for doing NN training maybe with 8-bitters and on-board, analog accelerators. My inspiration, aside from old MPP clusters (eg Thinking Machines), was a wafer-scale, analog NN done before Cerebras.
7. Improved reliability in general. In trusted checkers or fault-tolerant configuration, I feel like the 130nm parts are less likely to have a double failure or fail before the 7nm nodes.
8. If there's a business case, saying you built your own hardware is cool. It might even attract talent who benefit the company in other ways.
That's off the top of my head. Again, I just read a lot of stuff on ASIC's.
On a side note, you might find eASIC's Nextreme's interesting. They're Structured ASIC's that work like FPGA's in that design gets put on something with pre-made blocks to save money. Except, instead of software programmed, some via or metal layers get customized for the routing. While that reduces NRE cost, doing the routing in hardware supposedly reduces unit prices and energy maybe with a performance boost. They used to sample chips out quickly and relatively cheaply. Also, I think Triad Semiconductor had S-ASIC's with analog stuff.
I haven't paid that much attention, but in my utopia, they would have received some funding from the CHIPS act just to act as a gateway for educating people on how to design and make chips. But we live here.
America's such a technology hub because of our silicon foundry, because of MOSIS. https://en.wikipedia.org/wiki/MOSIS
Carver Mead & Lynn Conway got countless students & interested parties out there, making chips. Introduction to VLSI Design was a book, but also a whole practice of getting out there and doing the thing for real. So so so much innovation & creativity followed.
Efabless felt like such a great hope that the tradition could continue, that maybe perhaps we could have a new age of newcomers also starting to make chips.
And you can still use all the open source stuff, like the eFabless pad frame, if you want. But you’ll have to work with SkyWater directly which does require various business agreements to be in place.
See more here:
https://www.skywatertechnology.com/technology-and-design-ena...
The problem is access to software and fabs. EDA is expensive and nobody will give access to individuals. Same for fabs. They don't want to give access to a lot of people due to IP theft risks. Anyone can be a North Korean hacker. Plus they operate under US export controls which makes the paperwork daunting.
I assume they require an NDA for their PDK? Or can projects still be meaningfully open-source with the existing one?
https://www.skywatertechnology.com/first-google-sponsored-mp...
https://github.com/google/skywater-pdk
There's a bunch of other PDKs running around now too. But progress does seem to have distinctly tapered off.
If you know the right person, TSMC also has an MPW service (as do most other foundries). Most of the slots on these services go toward high-volume customers and universities, especially at the high-tech PDKs.
Other low-cost (at least low relative to the huge costs of silicon fabrication) services exist but typically they have little public information and will certainly require proprietary tools and PDKs (which are not cheap and require you to persuade the sales people to talk to you to even find out what these costs are).
If you're talking about how much it takes to build the fab: infinity dollars, nobody builds new fabs in these nodes anymore. Skywater is barely keeping its head above water as-is and that's mostly wafer services, not tapeouts.
Not infinity, so time to start saving up... lol =3
https://media.ccc.de/v/38c3-the-design-decisions-behind-the-...
Video from 38c3 talk 2024-Dec-29; question at time 31min:17sec.
This company, and its enablers (formerly) at Google, set back the progress of open source chip design by at least three full years with this bait-and-switch insanity. The people who could see through the ruse wouldn't touch it with a ten foot pole; meanwhile it sucked up all the students, momentum, and funding.
Think about what three years of progress is worth in the tech industry.
Caravel is fully open source. You can audit it. There is no ROM (except for a project ID), just 1.5KB of RAM, a CPU, a few peripherals and (most importantly) the pad ring.
Caravel is a (questionable) attempt to lower the barriers of entry to silicon design, both the cost and required skill.
It lowers cost, because every single chip on the MPW is the same size, and can be tested with a common interface. They can test the RISC-V core and pad ring to get a good indication of the die quality (theoretically they can upload user-submitted code to test the actual design, but I don't think have implemented that), and only package up the highest quality dies that are most likely to work.
It lowers required skill, because the user doesn't have to worry about getting the pad ring right. When they receive their chip, they are guaranteed to have a working RISC-V core, and caravel provides a bunch of logic analyser probes you can hook directly into your design to debug why it's not working.
It also meant anyone who actually wanted a CPU core in their design got something that was guaranteed to work and easy to integrate.
The Caravel harness makes it very clear what the target market for the eFabless product is. It's not for end products, you only get a few chips. It's for people, especially hobbyists to learn how to do silicon design. (Though, IMO it's nowhere near cheap enough for that target market.)
If you want an actual end product, you should be contracting either with eFabless or directly with Skywater for a full wafer with a custom pad ring.
in theory only.
caravel had hold time violations and the pin configuration mostly didn’t work for the first 5 or 6 sponsored OpenMPW shuttles.
My understanding is that there were problems with the whole Open PDK, and that most designs would have run into similar issues even if Caravel wasn't preventing IO configuration.
The didn't ship those early OpenMPW runs out at all, the designs where resubmitting to later runs. In a way, the incident proves the point: Caravel allowed them to quickly prove their yield for those early shuttles was essentially 0%, without needing to test the user design.
To clarify, since unfortunately griefers are flagging your comment to impede the discussion, so I'm not allowed to reply to it: Tiny Tapeout is a multi-project chip, not a multi-project wafer (though it is one chip in a multi-project wafer). Typical minimum die sizes are 0.8mm², which is about 2 million potential transistors in 130nm processes. That's big enough to put many projects on a chip. That's why Tiny Tapeout cost US$300 while MPW prices start at about US$3000 and more typically US$9999+.
The Caravel management engine is used for single project chips, but it is innocuous. It just allows debugging and probing signals, and use of common I/O structure for different user projects. You don't have to actively use it.
It's hardly hidden, too: you have to instantiate it.
The only even slightly uncivil thing about it would be the implication that I didn't know what MPW was, but in fact that was entirely plausible and would have been an important lacuna to correct were it true.
It was an exemplary comment, and the people who flagged it so that I could not reply were being a pain in the ass for no reason.
They cut the wafer apart into individual chips. There is one project on each chip.
This has been going on since the 1970s. It is a very well-understood process.
Over the past year they tried an experimental "multi-project chip" (first samples shipped 14 months ago). But the management engine was a requirement long before this happened.
GP seems to have edited their comment, but I can't edit mine (even though it is only 8 minutes old)
