Basically yes, but you have to generate the GDS-II from your Verilog yourself, you have to pay them several thousand dollars, the turnaround time is nearly a year, and your first and maybe second and third tapeout will probably have bugs that keep it from working at all.

There are open tool chains that will compile your design using the cells defined in the outreach programs fab specific standards. However, it will not necessarily function like your simulated hardware design.

Getting the hardware cell simulation working is not trivial, and Synopsys charges more per seat than most startups spend on labor in a year.

YMMV =3