> At the workshop, people asked me what it would cost to make a chip with SiFive. The room went quiet … people expected me to dance around the topic (like all other people do). Jaws dropped when I simply said “system architects and designers can get customized chips for less than $100,000” – less than the cost of just licensing most CPUs today.
[1] https://www.sifive.com/blog/custom-chips-for-under-100k
Say one lone developer gets a bit carried away with verilog and ends up with a description for a chip. I know there's an odd lot style of thing where you can get your chip drawn on a wafer along with a load of other chips from other people. There's probably a way of getting someone who knows what they're doing to attach wires to it, wrap it in plastic or whatever else is involved in "packaging".
Where does one get started with that, and what's the ballpark cost? I'm assuming a fair amount of the OP's $100k is SiFive labour, but I don't know how to guess whether a half dozen custom chips in some sort of packaging is of the order of 10s of dollars or 10s of thousands.
(edit: I've done a lot of software near hardware and have a vague idea that uploading the data to tsmc was called "tape out" and involved quite a lot of money, but I also vaguely remember talking to someone at a conference who had chips made as a hobby so there are some pieces missing from my mental model)
For example: https://efabless.com/chipignite $10K for 100 packaged dies in QFN. Which is not totally out of hobby range (I've seen people spend way more on fixing up cars that have no business being fixed) and if you use their harness they'll solve most of the hard EE problems for you.
But you might consider why you're making the IC. If it's for the experience, sure. But if it's to make a commercial product, there's a lot more to it. For example, what's your IO solution...
A friend recently discovered that PCBs can be ordered online for essentially zero cost and arrive in the mail and that surface mount soldering is an easy thing. Combined with a path for code to magic sand that's a whole world of dubious past times suddenly available.
Overall, the plan is much like OSHPark. You build a die that can be paired up with all of the other customers for a run. If say 300 wafers are made with 1000 different designs on it, everyone gets 300ish chips (before errors) and 1000 designers are happy.
*Made up numbers of course. I'm not in the business.
That's not how it works. The same pattern, called a "reticule" [1] is duplicated 300 times over the wafer. One wafer gives you 300 copies of whatever set of dies fit into one reticule.
[1] it's to do with the size of the optical/UV lenses that are used in mask-making
That's true but they keep upping the capabilities of what the designer can do at 180nm. Based on the wait times for my jobs, there's not a lot of spare cycles, at least at the foundries I use.
Its more likely that 180nm fabs are idling so much that they've made the decision to close. There's only so low that the prices can go before these businesses don't think its worth staying in business anymore.
I've heard that over the long term, 28nm should theoretically be the "long term cost-efficient node". The 65nm and other nodes are all cheaper in practice because these factories are fully paid off by now.
It was something about 300mm wafers and overall tooling being shared with 28nm with the latest nodes + overall investments. While 200mm likely will be shutdown over the long term (but 200mm wafers will remain the cheapest solution in the short term).
So under these expectations, I'd say that 180nm, 65nm, and other old nodes will slowly shut down as everyone moves to the long-term most efficient node. Still, having the oldest nodes stay open for the educational / hobbyist / experimental R&D for some commerical companies makes sense. Especially since the wafers are smaller and thus overall runs can be smaller.
If you could give SiFive your desired peripheral or custom instruction already integrated with Rocket and working on an FPGA (Arty) then you'd get it for under $100k for sure -- if you made SiFive do the work it would rapidly get to be more.
Disclaimer: I was an early customer for the HiFive1 (December 2016) and then worked at SiFive from early 2018 to early 2020, but I don't speak for them.
So, for example, if a business sends SiFive $100K and a copy of OpenRISC, they would receive ~300 chips that could then be used in a commercial product?
If a business then wants to order another 300 chips (or more), would they only need to pay SiFive the $30K? Does the $30K price fluctuate? Does E31 core have an end of life? In the event that EOL is reached, or SiFive ceases to exist, can the business make these chips somewhere else or are they screwed?
All that said, if you’re exploring, have fun! If you’re getting serious I’d recommend you find someone who can help you navigate it; there are many surprising things to learn as you go.
For instance, to answer your question on chips: all chips are made by ‘taping out’ - a process that yields the masks that can be used to make chips. These are only good with a specific chip maker, and will live with that chip maker near the hardware that is used to make the chips forever. It’s expensive to design the chip, and expensive to tape out, but once you have something it’s relatively cheap to make more of them.
180nm is potato quality - many many generations behind. So far behind it might actually be more expensive to get chips than at 110/65nm, although I’m only speculating here.
A shuttle run means the vendor is going to put your chip designs onto a wafer with a bunch of other ones at the same time; it’s a way to share out the costs for a tape out with other customers. The general idea of a 180nm tape out is likely that you want some parts to test in your infrastructure / build ahead of your full launch. Think of it like a compile with -debug turned all the way up.
Usually you’d then either adjust the design and re-do a shuttle run (your compile turned up real problems or your use case changed), or you’d shrink and make your own wafer, (turn on optimization and compile for deployment). Shrinking from 180 to 110 or 65 is likely almost totally an automatic process these days; as you go smaller, analog physics makes this challenging.
So, upshot: you probably could ask for another shuttle run, but you’d have a higher part cost than your first run because you’d be paying for the whole wafer alone this time, but only able to use the part that has your chips on it.
And, you’d need to be in a world where you really wanted another 300 chips of the same potato speed (and possibly quality) as your first run. Most likely a silicon consultant would find a more efficient use case for your needs, whether that’s a small geometry FPGA that is programmable, an existing chip (there are A LOT of chips in the world), or some other solution.
Anyway, have fun if you get into it — fascinating world.
As for "can you order more if SiFive goes out of business": the detail here is going to be in all the other bits on the chip. Maybe they're free licensed, maybe they're not. You probably wouldn't get the GDSII that SiFive sent to the fab. You'd need to arrange another shuttle run. You might be too small for the fab to return your calls.
It's a pretty niche kind of manufacturing activity. Not many businesses really need a custom CPU.
180 nm fabs are getting to the point where replacing machines is prohibitively expensive and spare parts have to be custom made.
I mean that is year 2000 level-tech. PlayStation 2/Pentium 3/AMD Duron/GameCube levels. That is not potato. You can definitely do things with it.
Plus SiFive divested their chipmaking division, OpenFive (formerly Open-Silicon) in 2022. That would be who you'd want to talk to.
This isn't want SiFive was doing - they're providing engineering expertise. Here you're allowed to put together all your own logic gates into... a thing.
The typical project is more like a binary counter, or a BCD to 7-segment decoder.
I don't think you would even be able to fit a 6502 -- not the core, but also you can't have that many pins.
I think one was done with a bit-serial SeRV RV32I CPU (which is 125 LUT6 and 164 flip-flops when done in a Xilinx FPGA), but without the CPU registers fitting on the chip.
[0] https://flyingcarcomputer.com/posts/a-new-personal-computer/
Regardless, respect. Seems daunting, but will no doubt be a really cool project.
