At a minimum, I'd like to see 4 P-cores and 4 E-cores plus 8 CU (preferably 16-24 CU).
This makes no sense to me. Lower die area means smaller feature sizes (ie a process size change) or fewer transistors (ie features change). I’m not sure how you have the same features in a smaller die area and (presumably) be at the same process node and “just” sacrifice clocks.
Do you have a source for that? Or more information about how that is possible?
Are the GPU cores that necessary?
All in all a weird showing, but not entirely unexpected given how long AMD has avoided big.LITTLE for.
Gives them a way to squeeze more money out due to less wasted defective chips.
Give us the power or give us the energy savings, this hybrid is both the best AND worst of both worlds.
They surprised me, as they don't look like "adjusted layout for different process options", as the 4c variant has been previously described in the press. Instead it looks more like "chopped off entire controller or coprocessor subsystems, and also shrunk a tiny bit"...
Don't think AMD has such a thing consider their all cores are "equal" approach.
Wouldn't you want that everywhere? Same perf but smaller means less cost for AMD yes? Bergamo was excused as "this is just for high density since we have existing chios for medium density" but if you are making new chips why not use the smaller but equal one?
It isn’t the same peak performance in the desktop, but it can be the same wide-scaling performance on highly threaded web server or database loads.
