Nvidia R&D chief on how AI is improving chip design (opens in new tab)

I guess so, but the fact of the matter is that ML/AI is actually, right now, doing useful things that would have been impossible 10 years ago. I don't think I could say the same about crypto (as distinct from cryptography).

> "AI" has been used to market so much nonsense it's probably becoming a problem communicating actual interesting uses of AI.

On the other hand: if the people who do serious work in this area don't call out this nonsense, they must accept that their (serious) work becomes devalued.

> It's very much the sort of problems crypto is having. So many grifters actual interesting uses of the technology are very hard to identify and take seriously.

Here, the same holds.

Yes, the way I see it, one of the major benefits of deep learning is that it lets you define functions (in the R^n -> R^m sense) that would be basically impossible to define with traditional programming techniques. I think this comes up a lot in subroutines of combinatorial optimization, like heuristics for guiding search on subsets of NP-complete problems. The fact that you can automatically evaluate the heuristic and train by RL is also very convenient.

In general, a function approximation solution like deep learning does worse on cases where exhaustively finding the exact optimum is possible (small combinatorial problems), but can be applied to much larger instances than the exact algorithms can.

Netscape.

Worked out great for them /s (albeit writing was already on the wall for them by that point.)

> Do you have an example of a company releasing an open source version of their secret sauce?

The chip design itself should be the secret sauce. Not the tools you make the chip with. Nvidia is resolutely not-contributing. Many other companies are starting to get onboard with open chip design. This doesn't mean the chips have to be open, but the tooling needs to be something shared & co-developable. If this is a little pet research project that's one thing, but there really needs to be ongoing workforce development, a strong advance. The NSF's TILOS, a strong alliance/nexus of researchers within & around the OpenROAD community, get this[1]:

> TILOS – The Institute for Learning-enabled Optimization at Scale – is an NSF National AI Research Institute for advances in optimization, partially supported by Intel Corporation. The institute began operations in November 2021 with a mission to "make impossible optimizations possible, at scale and in practice".

> There are six universities in TILOS: UCSD, MIT, National University, Penn, UT-Austin, and Yale. The institute seeks a new nexus of AI and machine learning, optimization, and use in practice. Figure 4 shows four virtuous cycles envisioned for the institute: 1. mutual advances of AI and optimization provide the foundations; 2. challenges of scale, along with breakthroughs from scaling, bind together foundations and the use domains of chip design, networks and robotics; 3. the cycle of translation and impact brings research and the leading edge of practice closer together; and 4. the cycle of research, education, and broadening participation grows the field and its workforce.

The virtues written here are self evident & obvious. Trying to just get good yourself without trying to help advance the field, not participating, not taking advantages of scale of many working together, not participating in open research, the risks of having isolated teams, and not participating in cycles of development: whatever the nvidia or "publicly traded company" worlds think they're doing, they're missing out, and hurting everyone and especially themselves for this oldschool zero-sum competitive thinking.

There are plenty of company's releasing the chips too. Google's OpenTitan[2] security chip. WD's Swerv RISC-V core for their driver controller ARM R-series replacement[3]. Open standards if not chips like UCI for chiplets or CXL for interconnect are again examples of literally everyone but NVidia playing well together, trying for better, standardizing a future for participation & healthy competition & growth. Nvidia again and again is the company which simply will not play with others.

I challenge you to answer your own question in reverse: are any companies other than Nvidia embarking up AI/ML chipmaking in a closed fashion? There probably are, let's follow & watch them.

[1] https://theopenroadproject.org/news/leveling-up-a-trajectory...

[2] https://opentitan.org/

[3] https://github.com/chipsalliance/Cores-SweRV

> Having a lead in chip design is their literal bread and butter

Sounds tasty, I'll have to take a trip to the nvidia cafe some time =)

IIRC, Place & Route is a known NP complete problem. In this regard, autorouters (whether IC or PCB) can benefit from "better" heuristics -- i.e. it's an optimization problem where AI can help.

Are the analog parts (current nitrist etc) autorouted now?

I worked on MCU layout around 2011, and only the digital logic was autorouted/placed.

> Can you explain why such large numbers are required?

Absolutely.

Even if you start with 32 bits, you often have polygons with many sides. In the worst case, you are modeling a "circle" and have to increase your precision to enough level to be accurate (please note that nobody in the right mind in VLSI would ever draw a "circle"--however, you wind up with an "implied" one due to DRC, more down below ...)

The problem is that line sweep intersection checks in DRC require approximately 3n+a couple bits to differentiate intersections that may be close to degenerate or have multple intersections near to each other. So, if you start with 32-bit numbers, you require approximately 96 bits plus a little for your intermediate calculations. (See: Hobby -- "Practical segment intersection with finite precision output" -- I'll let people find their own copy of the paper so HN doesn't splatter some poor site that I link)

You would think that doesn't matter since VLSI tends to limit itself to rectilinear and 45 degree angles. Unfortunately life isn't that simple.

If you take a simple rectangle and say "Nothing can be within distance x", you get a slightly larger rectangle parallel to the sides. Easy. The problem is that you also wind up with an implied quarter circle (told you this would come back) near each corner. Not so easy.

Put those circles such that they overlap only very slightly and you may have segments that are pretty close to tangent. Super not easy. Unfortunately, VLSI design often consists of putting those metals such that they are riiiight at the limit of spacing. Consequently, your super-not-easy case also becomes a very common case. Ouch.

Of course, you could just move the rectangle completely outward so that you have squares at the corners. However, that gives up a non-trivial amount of area that most places aren't willing to concede.

There is a reason why Siemens (nee Mentor) Calibre is so egregiously expensive.

> The resolution with 64-bit floats (let alone integers) would be absurd, roughly a million times finer-grained still.

Careful there! Floating point numbers do not form a proper field, not even a semi-group. Due to the uneven distribution of elements, the field axioms don't hold (e.g. both commutativity and distributivity can be violated) and great care has to be taken to assure the numeric stability of computations.

"as of 11.5, CUDA and nvcc support __int128_t in device code when the host compiler supports it (e.g., clang/gcc, but not MSVC). 11.6 added support for debug tools with __int128_t."

See:

https://developer.nvidia.com/blog/cuda-11-6-toolkit-new-rele... https://developer.nvidia.com/blog/implementing-high-precisio...

Having worked in EDA myself, though not on these final signoff steps, I agree that purely geometry-based checks really don't need doubles. Most of it should just be done as 32-bit fixed point. Both because it's better for performance, and because it drives home the point that you need to think carefully about precision issues for correctness reasons. Using doubles is just a band-aid.

I'm less confident about it when it comes to anything that involves calculating anything electromagnetic because I just don't know that subfield.

I think that's the point GP is making with his sarcastic remark :)