Dennard's scaling is long dead[1]. Density increases thanks to "3D" integration, but transistors do not shrink much. Thus more innovation needed in the areas you highlighted to make a "smaller" equivalent process node.
FinFET and GAA do achieve slightly better electrostatic control which results in lower leakage and slightly faster switching speeds, but gate length doesn't decrease much anymore, which puts a ceiling on switching speed improvements (thus frequency - GHz), and gate capacitance (linked to power consumption).
Increasing densities mean more avenues to explore specialized circuitry and dark silicon. Basically, more transistor to play with.
This is running very contrary to the previous paradigm with Moore's Law, in which specialized circuitry and specialized accelerators were not too deeply investigated as software implementations would gain so much performance that they would easily surpass them, while not needing to be redesigned for a newer node.
I'm now hoping for (and expecting) a revolution in maskless lithography at some point. That would democratize ASIC design (at 14nm, current multi-project wafers prototyping costs are around 10k€/mm², largely due to mask manufacturing), and make it much easier to explore the third dimension (thus making everyone more competitive with last gen).
[1]: https://en.wikipedia.org/wiki/Dennard_scaling#Breakdown_of_D... (although that article is a bit terrible).