> However, when mentioning the "nanometers" process node as evidence for scaling (it was unclear to me whether you said that it implied shrinking, or there had been some shrinking in between the two),
No, my intention was actually converse of that, saying that transistors still shink, even in leading edge nodes today, despite popular perception.
> I feel like I have to mention that transistors haven't been meaningfully shrunk for years, although there have been plenty of innovations regarding their layout, and photolithography processes have gained in precision.
TSMC 7nm->5nm increased transistor density by 80%. There were other changes to minimum cell size too, but both are 6T in this case so the overall device that can operate as a transistor in a VLSI does absolutely shrink.
Dennard scaling ending isn't about not shrinking, it's about power density going up. Even then things are not standing still, practical designs absolutely get denser and do more work even in the logic parts of the design. It's just doesn't double every couple of years anymore.
