Verilog originated in 1984 and educational institutions have been teaching it roughly as long, multiply by how many students graduate each year in an EE-related field and I'm pretty sure the number is far more than that in India alone.
Of course, the number of people who know Verilog (and Factorio) enough to implement something like this is going to be a fraction of that.
[1] https://github.com/Redcrafter/verilog2factorio/blob/9691b702...
[2] https://github.com/Redcrafter/verilog2factorio/blob/9691b702...
And I guess the reason that most tooling focuses on Verilog is that the VHDL standard is a little bit of a mess from a parsing point of view. Essentially, in order to correctly parse some VHDL file A you first need to parse every other file that A might depend on. [2] Source: Tried writing a VHDL parser a few years ago.
[1] AFAIK you can buy a license for a VHDL frontend from one of the companies contributing to Yosys, but that's a different story.
[2] Example: What is f(1)? It could be a) calling a function called f with a parameter_association_list consisting of 1 or b) an indexed name, accessing an array called f at index 1, or c) some other things if we're not currently in an expression context. The only way to parse this correctly is to know what f is, but if f is not defined in the file you're currently parsing, there's no way to know other than parsing all other files...
At least that is how I understand the market division, it might also be that one of them has already won, not sure about that.