Well, to be fair, if that's true, that's an improvement over 10^2 - 10^3 write cycles is what current NAND-flashes can manage. 10^12 is enough for it not to ever matter.
No, that's a low enough number that wear-leveling logic will be needed, as with flash memory. This is a fast device, approaching DRAM speeds. A program could easily bang on a cell 10^12 times.
