Far from a well-established point, and please do correct me if I am wrong, but ever since some point around 2008, the performance gain from CPU upgrade becomes kind of stuck, which sticks to around 10%-15% between generation.
Good abstractions come at a cost. You'll need more CPU power, but it becomes easier to write, read and maintain your code.
If performance becomes an issue, rewrite the critical sections to make less use of abstractions. If performance is a massive issue and it's not doable in a high-level language, then don't use a high-level language.
If CPU power stagnates, it doesn't matter. There is, and always will be, a place for abstractions, no matter what overhead they have.
JavaScript is very efficient in some respects: it trades off speed and memory usage for programmer productivity, safety, security and portability.
I don't believe this has to be true in the future (in fact, I'm not sure I believe it today either). This is a meme that we tell ourselves because we haven't invented clever enough programming languages or abstractions yet. This is exactly what I was referring to in my post. We as an industry would have to solve these problems at a fundamental level.
Take for instance manual memory management. People used to think that dynamic languages make this so much easier, but it has become much easier to write GC free programs (see C++11 and Rust).
I want to see more efforts in this kind of direction.
> JavaScript is very efficient in some respects: it trades off speed and memory usage for programmer productivity, safety, security and portability.
I take issue with this. JavaScript it is not a productive language at LOC scale. Security is par for the course. Modern systems languages are no worse or better. Portability I'll grant.
In fact I've yet to see java server-side stacktrace that's less than 100 lines long. Usually it's more like 1000 lines, with a few RMIs inside. On the other hand, the js stacktraces I've seen (mostly hobby projects, so I may be biased) are usually less than 50 lines, often just 10 or so. Not good, but much better.
gallium arsenide (GaAs) has six times higher electron mobility than silicon, which allows faster operation... Conversely, silicon is robust, cheap, and easy to process, whereas GaAs is brittle and expensive, and insulation layers can not be created by just growing an oxide layer; GaAs is therefore used only where silicon is not sufficient.
-- WikipediaStatic RAM cells haven't scaled for about two generations now, but you could still scale functional transistors.
Now, even that is stopping. Moore's Law was more an economic law than a physical one.
Exponential growth has to run out sometime.
I don't know.. people said the same thing when clock rates got close to 4Ghz. We always seem to find ways to work around physical limits.
I don't see that as a bad thing. There's plenty of optimization opportunities on the software level. Think of the difference between first-generation and last-generation console games.
http://spie.org/AL/conferencedetails/alternative-lithographi...
I would bet that improvements will become less predictable, though. Unfortunately, investors really dislike unpredictability, so R&D spending will probably drop.
Moving to more complex 3d chips could help improve performance, but there are limits to the number of dimensions we have too.
https://en.wikipedia.org/wiki/Bond_length
The lattice constant of unstrained silicon is 0.543 nm.
[1] https://news.ycombinator.com/item?id=9092506
[2] http://spectrum.ieee.org/semiconductors/devices/the-status-o...
That is the move from 22nm to 14nm did not give you double the transistor count from the same area die.
So has anyone done a comparison of transistor count on the same size die over the years depending on the process?
There is an interesting debate about feature size though. Devices on silicon for a long long time were essentially 2D, patterns on the top surface of Silicon. "Feature size" in this environment directly translated into area which directly translated into the die size.
As features got smaller you started getting 'trench fets' and other tricks to increase the effective size of the gates so that leakage current wasn't insane. So at what point then do the circuit elements become fully vertical, which is to say that viewed from the 'top' the transistor is 10 nm on a side but vertically its 22 nm 'tall' ?
And other tricks where the silicon layers are separately tested and 'thinned' and then packaged as a sandwich for final testing with ion implanters creating the vias between the connecting layers.
Really interesting work in that sort of stuff going on.