In my experience, make is coupled to Unix. Make is not coupled to C.
On the other hand, make can't cleanly handle #include dependency detection. I doubt that there is any major C project where "make extraclean" (or its equivalent) isn't occasionally necessary.
So yeah it's really not very well suited for C.
Or, you could use the C preprocessor option "-M" and its variants[0] to get it to generate make rules with C #include resolution for you.
See also Recursive Make Considered Harmful[1] for a good description on how to set up this in combination with GNU make's "include" facility to autogenerate your per-source #include resolution fragments.
[0] http://gcc.gnu.org/onlinedocs/gcc/Preprocessor-Options.html
Given it would be nice if make had a builtin macro to do this, but it is not too bad to type out.
depend: .depend
.depend: ${SRC} ${CC} -MM -I. ${SRC} > .depend.X && mv .depend.X .depend
include .depend
Makefile: .depend
However, implementations typically include magic that is heavily biased toward building C and C++ code. As someone who works on a lot of projects, some using those languages and some not, I tend to think it's rather too magical at times. Personally, I'd prefer to have that kind of magic explicitly stated in some standard file that comes with the tool, so that file can be included with a one-liner for those projects that want it but there is nothing implicit going on by default.
The rule applicable to C pertains to building foo.o from foo.c. It amounts to two lines in a Makefile:
%.o: %.c
$(COMPILE.c) $(OUTPUT_OPTION) $<
There are other rules useful for C++, and for yacc, etc., but they are just as simple.
You can cancel all the implicit rules with "-r", or cancel selected implicit rules by naming them in the Makefile like this:
%.o : %.c ;