Update on STM (opens in new tab)

(morepypy.blogspot.com)

138 pointswisesage500112y ago5 comments

5 comments

nn412y ago

Obligatory anti STM hype links:

http://queue.acm.org/detail.cfm?id=1454466 http://webcache.googleusercontent.com/search?q=cache:HhZcU_j...

Pretty much all the generalized (not functional) memory TM schemes with adequate performance rely on hardware acceleration. If your design doesn't support that your design is wrong.

kazagistar12y ago

Is there any plans to work hardware transactional memory into the mix?

kingkilr12y ago

Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.

4buser12y ago

Even new Intel Haswell's STM?

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