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0 pointschewxy12y ago0 comments

nah it's a different thing. He says general purpose processor architectures have so many rename registers because of single assignments. He then proceed to talk about percentage of data being Single Assignment.

Therefore, it's better to use a statick-sized queue structure. Hence "belt" - it's like a conveyor belt.

I'm still watching it though. The topic is interesting but man, his voice is droning.

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stormbrew12y ago

What he's talking about there isn't SSA. In SSA you never assign to a variable more than once. Instead you shadow the existing variable with a new version.

Converting to something akin to SSA (but not quite the same thing) is actually what he's talking about superscalar architectures doing in register renaming.

That said, just because you use an SSA IR doesn't mean your code generation doesn't require register renaming. But it would be a very good basis to generate code for this architecture.

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