Visualizing CPU Pipelining (2024) (opens in new tab)

Well, how about the Berkeley Out-of-Order Machine [0] (BOOM)? It's superscalar, out-of-order RISC-V design (one of the very first ones, in fact), and the documentation is fairly detailed. Read [0] and [1] for the general introduction, and then move down to the "Core Overview" section in the left navbar: "Instruction Fetch", "Branch Prediction", etc.

Also, here [2] is another, much more detailed explanation of an O-o-O implementation of a very simplistic RISC ISA which nonetheless has most of the relevant RISC-V features. There are also some other related texts on this subsite [3], including a single-cycle and a pipelined implementations, for the comparison.

[0] https://docs.boom-core.org/en/latest/sections/intro-overview...

[1] https://docs.boom-core.org/en/latest/sections/intro-overview...

[2] https://user.eng.umd.edu/~blj/risc/RiSC-oo.1.pdf

[3] https://user.eng.umd.edu/~blj/risc/

The article does say what it expects you to know before reading. However, it has a dead link to the knowledge it wants you to know.

Hi, I'm the author! Thanks for saying it's well made :).

I actually agree with you, the intended audience isn't someone who has never heard of CPUs before.

I tend to either write for myself: you know the saying you don't understand something until you try to explain. Or I'm writing for the person self-studying that is looking for that one explanation where everything finally clicks. I always get a lot out of those type of posts myself, so like to create them for others too.