Of course there's also the https://en.wikipedia.org/wiki/Vortex86#Vortex86SX , an interesting legacy from an era when there was far more competition in x86-compatible CPUs.
Hard to tell the exact ancestry of Lakemont. It might be a from-scratch scalar design that just so happened to target the i586 instruction set, but with a 486 style 5-stage scalar pipeline. Or it might be forked and hacked down from something more modern, like Atom.
It's a very configurable core. There are versions with just the FPU and NX bit turned off. MCU variant goes further, turning off segmentation, the BCD/string instructions, xchg and the AF/PF flags.
Intel did a talk on the MCU core at hot chips [1], which gives you a better idea of how they made/configured it (but doesn't give much insight into where the original Lakemont core came from).
But modern hardware design acts kind of like software these days. They write verilog code, they fork designs off, they share code or entire modules between teams. The code is often configurable. And then they throw the code + configuration at automated tooling which spits out reasonably good gate layouts.
The docs are written by completely different Technical Writing teams, who don't always fully understand the design they are documenting. They are usually correct enough for someone using them normally, but I've learned that relying on manuals to actually understand the underlying implementation (or its history) is problematic.
So reuse of 486 documentation doesn't prove anything. IMO it's more likely that the Technical Writing team saw how close the design was to the 486 and decided to re-use that documentation as the starting point.
CPUs today are so powerful and complex that it takes highly capitalized companies many years and generations to get something that approaches modern performance expectations. Arguably we’re still waiting for a RISC-V CPU to reach the market that has decent performance.
“it cannot have an FPU added (that is not the case with Cyrix 486S…)”
This is mostly true but the 486SX can be paired with a math coprocessor via the 487SX, but the 487SX is actually a full CPU that disables the SX, not a full FPU!
The 487SX is nothing more than a polite fiction to allow consumers (and the computer shops selling to them) to continue their existing habits of buying FPU-less systems, (because most people didn't need FPUs) safe in the knowledge they could buy the upgrade if they ever needed it.
It actually cost the motherboard vendors quite a bit more to wire up the second socket, so obviously there was demand for the flexibility.
