Regarding node sizes for image sensors, TSMC built a 28nm fab recently for Sony exclusively to make their latest sensors. There was actually a HN post about that a couple years ago [1]. Also, it's important to note that in many applications, the image sensor layer is now actually stacked, with a layer of DRAM (in 45 nm, for example) between, and a ISP (image signal processor) chip on the bottom made in a smaller digital process. You can see an image of that stack up here [2].
[0] https://image-sensors-world.blogspot.com/2020/08/tsmc-report... [1] https://news.ycombinator.com/item?id=24321804 [2] https://fuse.wikichip.org/news/763/iedm-2017-sonys-3-layer-s...