The other alternative is that you sprinkle spare gates around the chip. If the chip is 10mm x 10mm then every 100 microns you put a group of cells that just have their inputs tied to 0 and the outputs go nowhere. You put in a good mix of flip flops, and combinational logic cells. Then when you need to do a metal ECO the RTL team says "We need 2 AND gates, 1 OR gate, 1 mux, and they are connected to these 5 cells." So you highlight those 5 cells and find the closest spare logic group and use those.

The ECOFILLER gate array style cells are easier to use.

Then during the DRC check process in Calibre we run a check to make sure that the base layers stayed the same and only the metal layers changed. Since we have 18 metal layers in a leading edge node hopefully only metal layers 1 to 3 changed for the metal ECO so you only have to pay to make new versions of that.

A full mask set in 3nm can be over $30 million. Just a new set of metal masks is around $20 million.

A full mask run takes about 4 months in the fab. Normally you tell the fab to keep a few wafers after the base layers and don't manufacture the metal layers. Then when you do a metal respin they get those out of storage and save a month.