Related: I did not understand 95% of what she wrote.
- IC design software (at a startup bought by Cadence)
- an IC (contract out of Dallas semi)
- FPGA HFT acceleration
- fixing some OS drivers for Windows CE
- finding a compiler bug
- various bits of embedded firmware in C and assembly for various platforms
- debugging with a scope
- desktop applications
- a web server (defunct ZWS)
- web apps (Perl. Long time ago)
Somehow I've never written a react app.
Never got an offer through "who's hiring" though.
Is it true that we will likely have these 180nm chips for things like light bulbs for the foreseeable future?
Tape out time always sucks. I'm in physical design which is fixing all the timing violations, DRC violations, LVS errors, and dealing with late design changes.
Working 80 to 100 hours a week for a month really sucks and makes you wonder why you didn't go into software.
When you combine it with a fixed shuttle date like in the article it is even worse because if you miss that date it might be another 1-2 months for the next shuttle instead of just a day for day slip when you control all the masks.
I don’t work much on apps anymore but I hear it’s somewhat better now.
Another big area is compliance, those processes can take forever.
Lots of chips have metal spins to fix errors. The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of cell just by using metal. They are a little slower but work fine.
I've worked at one huge company where they planned 3 full base layer mask sets and 1-2 metal spins for each full base layer set. This was when doing a chip on a brand new process node where you couldn't always trust the models the fab gave you so you wanted more post silicon characterization to recalibrate models.
In case anyone wants a preview of what to expect.
I love the writing style!
Especially in the project roadmap section..
The licences for proprietary EDA tools are very expensive it seems and most EDA people i talked to didn't really care for any open source tools - as their companies paid for the licenses.
https://tinytapeout.com/chips/tt05/tt_um_rejunity_sn76489
https://librelane.readthedocs.io/en/latest/usage/timing_clos...
