I think that stemmed from their P-core design being shared between server and client. They needed AVX512 for server so they implemented it in the P-cores, and it worked fine there since their server chips are entirely P-cores or entirely E-cores, but client uses a mixture of both so they had to disable AVX512 to bring the instruction set into sync across both sides.

It’s a manifestation of Conway’s law: https://en.wikipedia.org/wiki/Conway%27s_law

They had two teams designing the two types of cores.