undefined | Better HN

0 pointsamszmidt8mo ago0 comments

Current work is at http://github.com/ams/cadr4

And of course .. https://tumbleweed.nu/lm-3 .

0 comments

rjsw8mo ago

Maybe try replacing the ALU with one written directly in Verilog, I suspect this will run a lot faster than building it up from 74181+74182 components.

amszmidtOP8mo ago

From what I see -- that is not the case.

The current state is _very_ fast in simulation to the point where it is uninteresting (there are other things to figure out) to write something as a behavioral model of the '181/'182.

~100 microcode instructions takes about 0.1 seconds to run.

rjsw8mo ago

I was thinking more of a behavioral model of the whole ALU, just so that the FPGA tools can map it onto a collection of the smaller ALUs built into each slice.

What clock speed does your latest design synthesize at?

1 more reply

j / k navigate · click thread line to collapse

0 comments

rjsw8mo ago

Maybe try replacing the ALU with one written directly in Verilog, I suspect this will run a lot faster than building it up from 74181+74182 components.

amszmidtOP8mo ago

From what I see -- that is not the case.

The current state is _very_ fast in simulation to the point where it is uninteresting (there are other things to figure out) to write something as a behavioral model of the '181/'182.

~100 microcode instructions takes about 0.1 seconds to run.

rjsw8mo ago

I was thinking more of a behavioral model of the whole ALU, just so that the FPGA tools can map it onto a collection of the smaller ALUs built into each slice.

What clock speed does your latest design synthesize at?

1 more reply

j / k navigate · click thread line to collapse