A Compelling Case for Using BSV (Bluespec SystemVerilog) in Academia (opens in new tab)

(incoresemi.com)

5 pointssaigovardhan1y ago5 comments

5 comments

Author here, When I joined InCore last year, I decided it would be meaningful to redesign my Undergraduate Capstone Project using Bluespec SystemVerilog (An InCore superpower) and contrast the efforts + compare the implementation with the legacy Verilog codebase.

This blog is an account of the same, with a walkthrough of the design, comparison results and steps to replicate.

Link to the GitHub repository: https://github.com/govardhnn/Low_Power_Multidimensional_Sort...

Lain_20041y ago

HLHDL's are clearly superior and is the way forward and there's no better way to prove the point than with real metrics on a real-time project absolutely loved the blog.

saigovardhanOP1y ago

Thank you! Yes, the purpose of this blog was to motivate peer hardware designers to switch to a much more intuitive HLHDL like BSV, especially in academia. This was my "skin-in-the-game" approach to travel back in time to the hardest problem I solved back in college (the MDSA Hardware Accelerator) and show how better/efficient I was in designing the same.

skudlur1y ago

Great blog op

saigovardhanOP1y ago

Thanks!

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5 comments

saigovardhanOP1y ago

This blog is an account of the same, with a walkthrough of the design, comparison results and steps to replicate.

Link to the GitHub repository: https://github.com/govardhnn/Low_Power_Multidimensional_Sort...

Lain_20041y ago

HLHDL's are clearly superior and is the way forward and there's no better way to prove the point than with real metrics on a real-time project absolutely loved the blog.

saigovardhanOP1y ago

skudlur1y ago

Great blog op

saigovardhanOP1y ago

Thanks!

j / k navigate · click thread line to collapse