Can some experts/knowledgeable folks here actually explain the technology in ELI5 (and above) terms? As i understand, a laser (what are its characteristics?) is fired at Tin droplets in a vaccuum chamber causing it to emit light in "Extreme UV" wavelength range which is then focused using a set of Zeiss mirrors to do the actual photolithography. Wikipedia (https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph...) is well over my head. What i am unable to bridge is how this EUV wavelength maps to transistor sizes (in nanometers) via High-NA/Hyper-NA technology.
From https://www.laserfocusworld.com/blogs/article/14039015/how-d...
A major limitation comes from the laws of optics. German physicist Ernst Abbe found that the resolution of a microscope d is (roughly) limited to the wavelength λ of the light used in illumination:
d = λ/(nsin(α)) ...(1)
where n is the refractive index of the medium between the lens and the object and α is the half-angle of the objective's cone of light. For lithography, substituting numerical aperture (NA) for n sin(α) and adding a factor k to the formula (because lithographic resolution can be strongly tweaked with illumination tricks), the minimum feasible structure, or critical dimension (CD), is:
CD = kλ/NA ...(2)
This formula, which governs all lithographic imaging processes, makes obvious why the wavelength is such a crucial parameter. As a result, engineers have been looking for light sources with ever-shorter wavelengths to produce ever-smaller features.
Explain the above?
Going further and further into the UV makes the wavelength smaller and smaller and thus the feature size smaller and smaller. But making light that is controllable in a way for photolithography techniques to work that far into the UV is the difficult part.
The minimum feature size that a projection system can print is given approximately by:
CD = k1 ⋅ λ / N A
k1 (commonly called k1 factor) is a coefficient that encapsulates process-related factors and typically equals 0.4 for production. (k1 is actually a function of process factors such as the angle of incident light on a reticle and the incident light intensity distribution. It is fixed per process.) The minimum feature size can be reduced by decreasing this coefficient through computational lithography.
According to this equation, minimum feature sizes can be decreased by decreasing the wavelength, and increasing the numerical aperture (to achieve a tighter focused beam and a smaller spot size).
Thus the NA being increased in Hyper-NA (0.75) from High-NA (0.55) results in a smaller "feature size" i.e. smaller nanometers.
I need to read some more but i think i now get the basic Physics concepts involved.
You may have heard the effect of light is like a wave, higher frequency wave-lengths have a shorter wavelength, which means it can 'reach' smaller features without impacting the rest of the surroundings. Photo-lithography is done through a mask, this effectively means you get a crisper image projected onto the wafer.
If you go too far into/past UV it becomes hard to deal with in terms of heat and optics from my understanding. Which is why we keep getting new $prefix-UV rather than something like X-rays (which are past UV).
Thanks for pointing me to this. This truly deserves all the views/recognition from HN/larger Internet.
The waves emanating from from that point would be spherically symmetrical (think a 360deg "field of view"[0], whereas most lenses are <<90deg).
Now, since optical paths are two-way, this also implies that forming a perfect point image requires perfectlu spherically symmetric wavefronts[1] converging to that point, causing all the waves to perfectly cancel out each other everywhere except at the image point.
If you take away a slice of the wavefronts (i.e. block light with an aperture), the cancellations is no longer balanced, producing stray excitations at places that should be silent. (Think of it like squeezing a beer can with your hand causing it to spurt out of the sides)
The large the slice of wavefronts you are missing, the greater the imbalance. The resulting artifact are oscillations on the size order relative to the waves' frequency.
Basically, high NA means trying to capture as complete of the total wavefronts as possible to minimize the imbalance, and short wavelength means trying to keep the size of whatever artifact you do end up getting to be as small as possible.
[0] In air quotes because FOV != NA. The main distinction is that FOV refers to the span of principal directions (i.e. how many points can you see), whereas NA means, given a point object, how complete of its total wavefronts are you capturing it, (i.e. how bright is any given one point)
[1] Up to 2pi phase differential. If your signal is CW then multiples of 2pi is indistinguishable from being in phase, think Shannon Limit. This is why lenses work despite having path differential, because all that's important is that it's back in phase for the given wavelength even if shifted by multiple cycles.
> Basically, high NA means trying to capture as complete of the total wavefronts as possible to minimize the imbalance, and short wavelength means trying to keep the size of whatever artifact you do end up getting to be as small as possible.
User "mk_stjames" pointed me to the answer which basically explains the equation for the above - https://news.ycombinator.com/item?id=40680072
This is a very fun subsystem diagram.
Then again, if they do an Intel 10nm+++++ and fail to maintain velocity even for a couple of years, their competition will close that gap very quickly.
(Serious question: I am just getting into the semiconductor world and haven’t found any competitors yet)
https://www.asml.com/en/technology/lithography-principles/le....
ASML is a Dutch company and is essentially a monopoly now that they first commercialized EUV lithography. They can essentially decide what companies live and die.
TSMC is probably ASML's largest customer because it reportedly produces over half of the world's chips. It is a Taiwanese company (and Taiwan accounts for two-thirds of global chip production). There is Intel too but TSMC have been way more successful in commercial chip fabrication in recent years.
TSMC is of course in Taiwan, which is way more politically precarious than Western Europe. A major disruption to Taiwan's production could be absolutely devastating. This is probably why the US is pursuing domestic chip fabrication (eg in Ohio with the CHIPS Act).
But having two companies with this much potential market influence has to make a lot of people very nervous.
It's a lot less concentrated on those two countries than it seems, but at the same time things are even more fragile than your post would imply.
TSMC has huge value, their R&D is hugely important. But if they vanished overnight, your G7 nation wouldn’t start to starve or anything.
Intel is trying to catch up but Samsung just has no idea. Samsung spent years poaching, merging and sniffing trade secrets to survive.
Problem with Intel is that most of it is Intel specific (still)
The US has viewed tech as strategic and a realm of competition with China since at least the late Obama admin (so 2015 or so).
Semicon as a key strategic goal for China is regularly mentioned in their 5 year plans in an extremely public way.
The US has leaned heavily on ASML to go along with export restrictions against China, along with a wide array of restrictions for e.g. leading edge GPUs and even CPUs. These restrictions have ramped up recently but they’ve been in place for years now.
Not only does this situation make policymakers nervous but they’ve been taking action. It's funny that the public has finally started noticing.
Odds are the US and Europe will never enjoy the comparative advantage Taiwan has in the semiconductor supply chain.
What does that mean? One of the west’s key strategic advantages is the ability to lead in frontier compute technologies. China, in addition to rapidly working its way up the value chain and nodes, can easily mitigate much of this advantage if it deems the calculus worthwhile. It need only disrupt Taiwan and basically all leading edge fab capacity is off the table. Outside of the work Intel is doing, the US does not have leading edge fabs.
We do not have the skilled workforce or supply chain to take advantage of leading edge fabs.
Why is this situation with Taiwan so difficult to unwind? In the West there is a fantasy that if war breaks out, we will just load all the Taiwanese onto a starship and bring them over to the US where they will happily resume their work in OUR fabs. But they don’t want that. They want their home and ideals to be defended, and they’re willing to do the work… from their soil.
The reality is the fabs are bargaining chip with the West, far better than any iron dome. The question becomes, how did we get in this position? And the answer is deliberately. The US saw putting semiconductor production in Taiwan and a way to reduce cost and challenge the Japanese, but also a way to imbed incentives into our foreign policy for protection of tenuous Taiwanese democracy and independence.
We have known this for a very very long time.
“There are new materials which have a higher mobility for electrons,” [than silicium]
https://en.wikipedia.org/wiki/Transition_metal_dichalcogenid...