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0 pointsmort963y ago0 comments

Only one small part of the CPU actually understands the "x86_64 language". Most of the CPU executes a completely different, much simpler language, where instructions are called "micro-operations" (or µops). There's a hardware component called the "decoder" (part of what we call the "front-end") which is responsible for parsing the x86_64 instructions and emitting these µops. One x86_64 instruction often produces multiple µops.

You can change the mapping from x86_64 instruction to sequence of micro-operations during boot on modern CPUs. That's what we mean by updating the microcode.

At least that's my understanding, as someone who has implemented a few toy CPUs in digital logic simulation tools and has consumed a bunch of material on the topic as hobbyist but have no actual knowledge of the particulars of how AMD and Intel does stuff.

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9 comments · 3 top-level

nomercy4003y ago· 4 in thread

So the decoder is like an emulator. If so it would theoretically be possible to provide a different ISA and have it execute by the cops as well. Not saying it would be fast, or practically possible due to how locked down it is.

nick__m3y ago

Transmeta tried that approach, but it wasn't enough of a competitive edge for it to prosper.

imtringued3y ago

Transmeta couldn't bring their product fast enough to the market because Intel was suing them. It had nothing to do with the quality of the product itself.

Symmetry3y ago

Then NVidia re-used their design on ARM as Project Denver.

JosephRedfern3y ago

Is this kinda what thumb mode on (some) ARM chips is?

Const-me3y ago· 2 in thread

Micro-ops aren’t simpler than the AMD64 instructions, the complexity is about the same. For instance, the following instruction

    vfmadd231ps     ymm3, ymm1, YMMWORD PTR [rax-256]

does quite a few things (memory load, and 8-wide fused multiply+accumulate), yet it decodes into a single micro-op.

Most AMD64 instructions decode into a single micro-op. Moreover, there’s a thing called “macro-ops fusion”, when two AMD64 instructions are fused into a single micro-op. For example, scalar comparison + conditional jump instructions are typically fused when decoding.

mort96OP3y ago

That's an important detail, not all macro-ops are more complex than micro-ops, and most of our everyday x86 instructions are simpler than the more complex micro-ops.

But we can agree that the complexity ceiling is much higher on macro-ops than micro-ops, right? The µop you mentioned does one (vector) FMA operation on two (vector) registers and stores the result to RAM. While in x86, we have things like the rep instruction which repeats an action until ECX is zero, or the ENTER and LEAVE instructions to set up and tear down a stack frame. Those are undoubtedly implemented in terms of lots of micro-ops.

Const-me3y ago

> complexity ceiling is much higher on macro-ops than micro-ops, right?

Other examples are crc32, sha1rnds4, aesdec, aeskeygenassist - the math they do is rather complicated, yet on modern CPUs they are single micro-op each.

> one (vector) FMA operation on two (vector) registers and stores the result to RAM.

It loads from there.

> Those are undoubtedly implemented in terms of lots of micro-ops.

Indeed, but I don't think it's complexity. I think they use microcode for 2 things: instructions which load or store more than 1 value (a value is up to 32 bytes on AVX, 64 bytes on AVX512 processors), or rarely used instructions.

alex_duf3y ago

that makes a lot more sense now, thanks!

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