It's not a traditional FPGA chip (lots of luts and flip flops). The "AI Engine" is basically hardened chiplets that are working alongside soft logic chiplets and I/O. This is how they're able to get their performance/power numbers
I suspect that it still has some fpga fabric attacched to the ai engines. The two parts are separate, but according to Xilinx docs (talking about Versal Soc), they are supposed to work togheter
