There were some nice boards floating around though you may have to watch out for supply chain issues still plaguing this market. Examples:
- icoboard: has the 8k LUTs chip, comes with soldered PMODs[1], if you get it watch out as you either need a RaspberryPI with GPIOs soldered to program it, or you purchase their USB FTDI interface in addition. See: http://icoboard.org/
- iCEBreaker, comes with the 5k LUTs chip, has the USB-FTDI interface built-in, but you need to solder the PMODs yourself. See: https://www.crowdsupply.com/1bitsquared/icebreaker-fpga#prod...
[0] https://tinyvision.ai/products/upduino-v3-1
[1] https://github.com/FPGAwars/apio
[2] https://daveho.github.io/2021/02/07/upduino3-getting-started...
[1]: https://www.quicklogic.com/software/qorc-mcu-efpga-fpga-open...
[2]: https://f4pga.org/
Yosys functions more like a software open source tool. So command line compiling. It also has a REPL. It is very quick compared to the commercial solutions. Especially around compile times which can take seconds instead of minutes. YMMV, but I think the consensus is that it's a lot more convenient to use.
In general the hardware toolchains feel very ancient compared to software toolchains.
I could probably pick up Verilog now a bit quicker, I’d jump straight to system Verilog though if I did.
Ed. Seems it's in Verilog-1995, too: http://www.csit-sun.pub.ro/~duca/cn/verilog_ref_guide/vlog_r...
Do any vendors intend on supporting chisel? Does chisel have enough control to ensure generated vhdl/Verilog match the what vendors look for to infer certain things like certain ram and dsp instances? Does chisel have a fast simulator like ghdl?
I've used Chisel to interface with proprietary Lattice DSPs and RAM modules, and I'm sure you could do the same with other vendors as well. All you have to do is define the IOs and parameters of the module. In Chisel this is called a "Blackbox". Example: https://github.com/fayalalebrun/6502-exp/blob/master/src/mai...
Also there's a project called FireSim that can do cycle accurate simulation of Chisel on cloud FPGAs apparently at 10-100MHz which is pretty crazy!
IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end.
https://github.com/secworks/prince/blob/master/src/rtl/princ...
(Yes, I should really move the functions to a separate include file.)
The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.
Think of an ALU that can perform add, sub, shift operations. The ALU implementation simply accepts operands and perform one of the supported operations to generate the output. The control flow would in this case look at an opcode and decide which of the ALU operations to perform.
I chose Chisel (https://www.chisel-lang.org/) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation.
I'd highly advise looking into it although also knowing Verilog helps a lot.
