2. Connecting the body terminal to something other than the highest voltage is dangerous and we rarely do it except in switches and diff pairs. We'd never do something like this. You can't even connect the nmos body to the gate unless you're using "deep" nwells which is an expensive process step that most people seem to avoid these days
3. I hate it when foundries do this in their standard cell libraries. Its an extremely weak pulldown and I've seen problems in production caused by using this structure. You can make a much better structure with a third transistor and positive feedback where devices still aren't connected to the supplies, but you get a stronger pull.
4-6. These are current-mode logic, but you never see them made this way because they're slow and high power. Instead they're usually made with a tail current source on the "bottom" and resistors on top, which keeps all transistors in a faster operating region. They get used often in RF clock dividers.
16. Again, connecting the body is dangerous, especially when the potential is somewhat unknown, but this does get used in extremely low power/low voltage applications.
I didn't get through all of them, but it made me wonder - with two 4-terminal devices, how many possible configurations can you actually make?
Another perspective is that it would take a computer only a few minutes to generate all these circuits and test them for usefulness in a simulator.
For example the first circuit; the inverter; when Vin is low, the bottom NMOS is off, the top PMOS is on. And vice versa when Vin is at the high voltage suitable for the devices.
Statically this works pretty well. But the trouble appear during the transition of Vin between the two state.
Un the middle of the range both MOSFETs are likely conducting, effectively producing a dead short!
On silicon they will design both MOSFETs to control and reduce this effect as much as possible. If you attempt to reproduce this, you might be in for a magic smoke release moment.
I did manage to somewhat reproduce this without a constant meltdown with tiny discrete MOSFETs by using two tiny ones with the most complementary specifications as possible. The goal was to have them with the least amount of overlap in conduction with regard to their respective inputs.
This is exactly the configuration described in the CD4069UBE datasheet, where single stages of the hex inverter are biased to the midpoint with a feedback resistor. This turns them into a surprisingly good programmable inverting amplifier, rather like an opamp without a non-inverting input.
Using non well matched MOSFETs resulted in a rapid uncontrolled atomization of the MOSFETs.
And it's definitely used by real engineers. It's for making switching power supplies, so it can handle fairly complex circuits. I wouldn't venture into RF/high speed circuits with it though, since the included parasitics aren't sufficient.
And, custom functions are supported, so, I believe, you can put whatever maths in a component (I've never ventured this far): https://ltwiki.org/index.php?title=B_sources_(complete_refer...
Most EDA packages will include some sort of simulator, often SPICE-based. The fancier ones for RF work include or integrate with field solvers.
https://computationstructures.org/exercises/sandboxes/jade.h...
As far as the linked article "Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs", I will mention that CircuitLab does NOT currently provide a MOSFET model that includes a separate body terminal.
Instead, the body (also sometimes called the "back gate") and source terminals are assumed to always be internally connected in the CircuitLab MOSFET models, resulting in a three-terminal device.
Almost all real-world discrete MOSFETs you can buy are also three-terminal (gate/drain/source), not four (gate/drain/source/body). Some discussion here https://electronics.stackexchange.com/questions/137161/why-a... and here https://electronics.stackexchange.com/questions/185109/mosfe... but not especially satisfying in my opinion.
As a result, Figures 2, 16, 27, 29, 46, 49, and 50 can NOT currently be realized within CircuitLab.