I'd also like to see if this attempts to address the drawbacks of VHDL and Verilog. When I used VHDL in college in the 90s, I remember that it had a lot of trouble with basic stuff like describing a collection of bits as a variable and expecting math on that variable to "just work". Like maybe I could connect a circuit directly to one of the variable's bits, but it acted flakier than if I connected it to a verbose circuit described manually. I think it had something to do with timing, maybe rising/falling edge stuff, or maybe something needed to be latched before it could be used, etc. And maybe some of that has since been "fixed", although the problem was probably user error on my part.
Anyway, I'd like to see a thin layer above hardware description languages that takes care of that stuff so that they don't have surprising side effects. It's kind of like how XML is more powerful than JSON because it can have its own types, but the industry discovered that custom types encourage anti-patterns, so now everybody just uses JSON. I need a circuit to be built as described, even if it has additional training wheels inside for my protection, and then an optimization pass would remove anything superfluous or maximize stability by converting to stuff like gray code (which is probably already widely supported). I feel rather strongly that this issue has set FPGAs back by at least 2 decades, maybe longer.
As I explained it in another comment, this aims to make it easier and more approachable for learners to learn about hardware. I (personally) feel HDLs can be a bit scary, and as this is in a higher level language, you get its familiarity and still get to think about pins and their connections and stuff.
As you mentioned , this is indeed choose-your-difficulty library. You can make everything out of gates, or as I did in my CPU demo, expose pins for connections, but do the internal processing using if-else and loops etc. (https://yjdoc2.github.io/pcb-rs-examples/) This allows focusing on stuff like how caches are invalidated on jumps and how waiting on memory takes CPU cycles etc.
Currently this does not translate to something that can be targeted to directly h/w like VHDL etc does. But hopefully this will make subject of hardware and low level systems more approachable and easier to learn.
Thanks!
VHDL and verilog are definitely ugly, and MyHDL took a whack at trying to make it better... But this seems to come up a little short.
What this aims to is make writing and learning about hardware more approachable to newcomers or self-learners. This is still in a high level language (Rust) so you have some familiarity, but you still have to consider how to connect pins and stuff, so you can start thinking about h/w that way. This is in a way choose-your-own-difficulty, so you can write everything from basic gates, or as I have done in the CPU demo, you can define pins, but write the processing logic in high-level constructs such as if-else, loops etc. This makes it easier to focus (for the CPU eg) on showing stuff like cache invalidating and wait states for memory access.
Another thing is that this can be compiled to wasm, so you can make circuits and provide nice GUI like I have done for all my demo examples at https://yjdoc2.github.io/pcb-rs-examples/ . This way you can have interactive examples right in your browser which you can play with.
Again, yes, HDLs can do all of this, but I think they are a bit scary to approach, especially if you're learning this yourself / are a newcomer ; and I hope that pcb-rs will be a rung in the ladder making it a bit easier to learn about hardware and low level systems.
Hope this clarifies it a bit! Thanks!
Isn't vhdl more about simply formally and thoroughly defining it?
Can you play with ideas and check things out by just noodling in vhdl?
As far as I understood there is no functionality (yet) to translate it to something that could run on an FPGA.
