It's better, but still not the same level of timing guarantees. I suppose, left to right, you would have something like:
SBC/Linux -> SBC/Real-time OS -> General Purpose MCU ->
Specialized MCU (Parallax Propeller, for example) -> FPGA/CPLD/DSP
With perhaps some additions to the diagram to account for bit-banging vs actual drivers, speeds where some portion of the left side just isn't fast enough to even kind-of work, slow clock MCUs vs fast clock MCUs, etc.
