undefined | Better HN

0 pointsjolmg4y ago0 comments

I don't even see the issue. RISC-V is supposed to be a RISC-type ISA. It's in the very name. That it takes more instructions when compared to a CISC-type ISA like x86 is completely normal.

https://en.wikipedia.org/wiki/Reduced_instruction_set_comput...

0 comments

theresistor4y ago

The argument for RISC instructions (in high performance architectures) is that the faster decode makes up for the increase in instruction count. The problem is that a faster decode has a practical ceiling on how much faster it's going to make your processor, and it's much lower than 3x. If your workload is bottlenecked on an inner loop that got 3x larger in instruction count, no 15% improvement in decode performance is going to save you.

snvzz4y ago

Amount of instructions matters much less if they can be fused into more complex instructions before execution.

RISC-V was designed with hindsight on fusion, thus it has more opportunities for doing it, and doing it at a lower cost.

And, due to the very high code density RISC-V has, the decoder can do its job while not having to look at a huge window.

saagarjha4y ago

Ok, but where it the chip that can fuse these?

jolmgOP4y ago

I don't know what the design goals of RISC-V were, but I would guess performance is not the key goal or at least not the only goal. It makes more sense that ease of implementation is a more important goal, if they want to make adoption easy. That's another argument for favoring RISC over CISC.

monocasa4y ago

If that's the case, you can always stick a uop cache in after the decoder.

theresistor4y ago

To everyone who's saying "But macro-fusion!" in response, see my comment here: https://news.ycombinator.com/item?id=29421107

userbinator4y ago

Larger caches won't help much either; there's an old article I remember that compares the efficiency of various ARM, x86, and one MIPS CPU, and while x86 and ARM were neck-and-neck, the MIPS was dead last in all the comparisons despite having more cache than the others. RISC-V is very similar to MIPS.

snvzz4y ago

Larger caches, as seen in Apple's M1 L1, are one of many tools to deal with bad code density.

RISC-V might, at first glance, look similar to MIPS, but it leads in code density among the 64 bit architectures.

1 more reply

j / k navigate · click thread line to collapse

0 comments

theresistor4y ago

snvzz4y ago

Amount of instructions matters much less if they can be fused into more complex instructions before execution.

RISC-V was designed with hindsight on fusion, thus it has more opportunities for doing it, and doing it at a lower cost.

And, due to the very high code density RISC-V has, the decoder can do its job while not having to look at a huge window.

saagarjha4y ago

Ok, but where it the chip that can fuse these?

jolmgOP4y ago

monocasa4y ago

If that's the case, you can always stick a uop cache in after the decoder.

theresistor4y ago

To everyone who's saying "But macro-fusion!" in response, see my comment here: https://news.ycombinator.com/item?id=29421107

userbinator4y ago

snvzz4y ago

Larger caches, as seen in Apple's M1 L1, are one of many tools to deal with bad code density.

RISC-V might, at first glance, look similar to MIPS, but it leads in code density among the 64 bit architectures.

1 more reply

j / k navigate · click thread line to collapse