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0 pointsTaniwha4y ago0 comments

As the GP points out the problem you're up against is the tooling - to be mainstream a new language needs to be supported by the main commercial ASIC tool chains - synopsys/cadence/etc, the tools from each of the FPGA, as well at least one high performance compiled simulator (probably running on both linux and windows) - then you need coverage tools, linters or equivalents, plus you need to be able to access IP libraries in all the tapeout synthesis targets (which probably means mix and match with existing verilog and vhdl libraries and IP generators).

It's not impossible, but it is an incredibly big chicken and egg problem where most of the pieces are out of your control - the best you can do is to make highly efficient (ie synthesises well, simulates well) verilog or vhdl and hope enough people start using your tooling that the big vendors choose to implement your language as a target.

(oh and My (system)Verilog has far more types than just wire, is accepted by the big guy's tooling and generate allows me to avoid almost all copying)

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gnull4y ago

I'm trying to look at one specific component here, the language itself. My claim is that as a language Clash is way better than SystemVerilog.

True, Verilog has more mature tooling and is better supported by vendors at the moment. But most of it is because Verilog is old, and because hardware people have little knowledge of (and demand for) good programming languages; not because it's a good language (maybe it's better than the other even worse languages, but it's not good by the software programming standards). It's not that Verilog is somehow inherently good for implementing tooling for it, absolutely not better than Clash.

> far more types than just wire

You mean integers and C-style structs? “Far more” is a big stretch here. And these “types” are not very useful: they are only used to decide how operators should behave on values. As far as I remember, even Verilog's assignment doesn't care about types, as long as left- and right-hand side have the same number of bits, the assignment is allowed.

> generate allows me to avoid almost all copying

At the cost of: extra work (you're essentially implementing polymorphism by hand), inferior readability, increased risk of making mistakes, no support from the compiler. Generate can be almost perfectly replaced by code generation in Python.

Seriously, look at the way Clash allows parametrizing things, you will be impressed.

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