The person you're responding to isn't an FPGA dev (or at least not primarily). They're talking about verilog for ASIC design where the last step is is making the lithography mask that "tapes off" parts of the silicon substrate (like a painter tapes parts of a wall when painting).

I play in the space (Chisel and FIRRTL and CIRCT) so I agree with you but you're being far too dismissive of the people you're aiming to convert.

>But as a language Clash can do everything Verilog does.

Ironic since people say the exact same thing of Haskell and eg python and yet we still don't have wide Haskell adoption.

You have to deeply internalize that a PL or HDL is a tool. Thus, this position makes zero sense

>its ability to work together with vendor-specific tools and other ecosystem stuff, I don't know much about this

No one uses tools that don't fit somehow into their workflow. Further, if the users of the tool are happy with their current toolset then you have a very hard road to hoe in convincing them to adopt your tool.