If I recall correctly from my uni days, one of the big challenges with further shrinking the physical gates is that the parasitic capacitance on the gates becomes very hard to control, and the power consumption of the chip is directly related to that capacitance. Of course, nothing is so simple and I'm sure Intel can make some chips at very small process sizes, but at the cost of horrible yield.
The current state of the art seems to be 3D transistors (FinFETs, GAAFETs), which are one possible way to address the capacitance issue, and opens many design possibilities. It leads to other challenges though, for example heat dissipation.
