How much of that added density is used for what kind of performance and how much is used to prioritize efficiency is up to the chip designers -- for the M1 you get a couple cores that focus on performance and a couple cores that focus on efficiency, plus a lot of area for the GPU and a not insignificant area for the mysterious (to me at least) 16-core neural engine (aside: I wonder if e.g. the graphics pipeline is able to make use of that, as it seems like it should be able to perform matrix multiplications, and it'd be a bit of a waste if that just sat there most of the time).

So you'll probably see some variation but each time a process is scaled down to 0.7x of the previous size, you'll get smaller transistors that use less power individually and you could expect a "40% performance boost for the same amount of power and a 50% reduction in area" (according to https://semiengineering.com/5nm-vs-3nm/)

90 nm (2003) * 0.7 = 63 nm

65 nm (2005) * 0.7 = 45.5 nm

45 nm (2007) * 0.7 = 31.5 nm

32 nm (2009) * 0.7 = 22.4 nm

22 nm (2012) * 0.7 = 15.4 nm

14 nm (2014) * 0.7 = 9.8 nm

10 nm (2016) * 0.7 = 7 nm

7 nm (2018) * 0.7 = 4.9 nm

5 nm (2020) * 0.7 = 3.5 nm

To me, it's a bit of a miracle that Intel is still able to sort of compete on mostly 14 nm nodes, but maybe that's because "node size" basically just means "smallest feature size", and their 14 nm or new 10 nm process is a little better than e.g. competing 14/10 nm processes, or maybe their chip designs just prioritize different things that have a decent real world effect (e.g. Intel CPUs have AVX-512, but AMD CPUs don't).