Ask HN: Why can't we replace instructions in a binary for different ISAs?

> Different CPUs have different memory consistency models for parallel threads, leading to race conditions when translating

Does the race condition happen during the translation or execution? If it's former, we can somehow prevent it, right? The translation code is known.

> Anything with a JIT compiler (including most web browsers) needs special handling.

I guess this is something Rosetta 2 does.

From what I can tell, the listed reasons are mostly alongside how hard or challenging it would be but there is no actual technical limitation. It's just no one really made the effort, I guess because of QEMU since it works for most cases albeit with a performance penalty since it's emulation rather than translation.

Do you think it's feasible to implement a translation software that similar to Rosetta 2 but open source and covers other ISAs like RISC-V? I understand that it's hard but it's also surprising that while we see the barrier for different ISAs to be the compatibility but at the same time we settled for only runtime emulation.