I cannot disagree more strongly. Working with a hybrid software+logic project will teach you so much about both the similarities and differences between the two worlds.
CPU+software+fabric DMA+logic accelerator == win
My disappointment with the FPGA world is how stuck it is in the "emulate an ASIC" rut. These things, physically, could change their whole logic and connectivity design on the fly according to instantaneous requirements, but everybody assumes you have to load them up once at reset and leave them that way. Each switch-point setting is just a flip-flop, no different from any of the ones in the LUTs.
Manufacturers enforce this treatment by providing only serial access to the switch-point settings in their tooling, but there is probably a lot of room for more flexibility, at least in some.
Yeah, I'm not a big fan of this statement. Imagine if people said in programming, "Don't fall into the Rust/Python/.NET trap. Use Java."
On the other end you have beginners asking stupid questions like 'okay how do I print hello world using python on this FPGA?' instead of thinking about the digital logic design that goes into it. Which is why I discourage the beginners from using anything but HDLs.
If anything HLS can be a good tool for professionals who already know what they're doing and understand what they're giving up by using an inherently sequential (programming) language to model inherently parallel hardware. They are in a position to use it as a tool to rapidly prototype their design and make incremental improvements thereafter, not beginners.
> On the other end you have beginners asking stupid questions like 'okay how do I print hello world using python on this FPGA?'
And why is it not simple? Dogma? Industry standards? Drinking the FPGA vendor kool-aid?
What's wrong with having "print('hello world')" run on a micropython running on a risc V core on an FPGA? Because that's not an optimal solution? Are you serious? To me that seems like an awesome first step.
FMC tends to be big bulky & stupid expensive. PMOD is great for interfacing microcontroller shit, but this is FPGAs we are talking about. Throughput monsters with high speed serdes & rather fast regular io. These two longstanding options put you at a high very expensive end, or a pretty so so low density low data rate low cost end.
Which is silly. Everyone & their uncle is trying to push better high density connectors. Almost none have a community around them.
Very small & not a big community, but one example of an active much denser & higher throughput, there is syzyg.
Also just a about out to the incoming io specs. There's a very big win when we can get better at stitching together systems & cxl, ccix, opencapi, & gen-z are each massively compelling new io/coherency systems.
