> A Portable Architectural Protection Model ... We have experimented with adding the CHERI protection model to a number of ISAs, beginning with 64-bit MIPS, which was the baseline for our original research. More recently, we have developed an experimental version for 64-bit ARMv8-A (in collaboration with Arm), and also for 32/64-bit RISC-V.
Something that can work across architectures will see much faster adoption, I'm happy to see it.
Having something in the GHz range will give us a chance to try things we are currently struggling with, e.g. fuzzing is painfully slow.
prototype board to be available from late 2021
I didn't realize the wait would be quite that long.