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0 pointstyingq6y ago0 comments

That seems a bit harsh. You have to start somewhere, and this teaches basic stuff like an ALU, Clock, Accumulator, etc. Some homebrew CPUs have memory bank switching.

Moving to an FPGA based CPU might be the next step. There are soft CPUs with cache, MMU, etc. (https://github.com/SpinalHDL/VexRiscv for example)

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4 comments · 2 top-level

msla6y ago· 2 in thread

I don't intend to be harsh, but I am disappointed that there's apparently no ramp-up from the basics to a modern CPU design, that you get taken to some point where everything works but there's no path to stuff like out-of-order execution.

fizixer6y ago

So as I understand:

- H&P does a very good job of giving updating arch knowledge, but it's mainly "theoretical"

- In order to build/simulate modern arch features, a lot of work needs to be done.

So we have simulators like gem5. Do you think what's seriously lacking is, for some expert to sit down with H&P and gem5, implement a ton of modern features, analyze them, and write a big textbook about it along the lines of 'Practical Computer Architecture'?

msla6y ago

> Do you think what's seriously lacking is, for some expert to sit down with H&P and gem5, implement a ton of modern features, analyze them, and write a big textbook about it along the lines of 'Practical Computer Architecture'?

That would certainly help. Another good step in the right direction would simply be taking a processor with a good mix of modern features and giving a guided tour. Everything is done by something, so show all of those somethings and how they're put together, and how they all fit together into a complete design.

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namibj6y ago

The picorv32 project offers a RISC-V core that only lacks MMU/privileges, but the memory interface should make a cache quite easy to add.

The gate count won't be that bad, considering it's only ~700 LUTs in Xilinx 7-series FPGA. I think it'd fit in <10k gates, not counting the registers.

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