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0 pointsnickpsecurity6y ago0 comments

The other issue is that the older nodes are more reliable. They're already matured where they understand how to make everything work right. On top of that, each process shrink introduces new challenges that can cause components to fail. The most modern nodes seem like they make everything somewhat broken coming out the door with designers building in mitigations for that. They don't last as long.

The older nodes don't seem obsolete if component reliability is a concern. All my concepts consider their potential. They're quite limited in performance, storage size, and energy, though. There's a tradeoff. Lots of companies want a cheap, reliable, simple CPU/MCU. That's where the oldest nodes shine. That said, the newest nodes are tiny enough that one might make a 2 out of 3 setup with extra error correction like Rockwell-Collins' AAMP7G CPU. Might still be pretty cheap... per unit (not development cost)... on 28nm CMOS or SOI process. Haven't seen an attempt.

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kragen6y ago

I think Padauk is using 1.3-micron or something? Can't find my notes. I don't think you have to go quite that far into the stone age to get reliability, at least not for digital.

Do you have funding to do a MOSIS run or two? I wonder if we could find some.

nickpsecurityOP6y ago

No funding at the moment: researching on the side while working a main job. The older nodes for MOSIS were 350nm and 500nm. The fabs for these penny chips can be stone age in comparison. You're right that you don't need to go that far given the highly-reliable POWER's and Alpha's weren't built on stone-age nodes. Edit to add that, based on MHz I remember, the Alpha's were 350nm-500nm. Fits MOSIS well. :)

If you do a project, I suggest 350nm since it's the last node that you can visually inspect the resulting silicon. It's as fast as you go before you need electron microscopes and such. It's also more likely that the open tools for hardware will be able to handle such a node instead of deep sub-micron. Finally, there's old research in transistor-level optimization that might be applied to it in new, open tooling. Might let people do standard cell that inches a bit closer to performance and energy use of custom designs.

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kragen6y ago

I think Padauk is using 1.3-micron or something? Can't find my notes. I don't think you have to go quite that far into the stone age to get reliability, at least not for digital.

Do you have funding to do a MOSIS run or two? I wonder if we could find some.

nickpsecurityOP6y ago

j / k navigate · click thread line to collapse