The moment you're talking ASIC (or even FPGA, with an opaque bitstream), it's anybody'd guess what happens whether you use a RISC-V CPU or not. Even if the known CPU is known to be untainted, a tiny, invisible, additional CPU is sufficient to take over the chip and you'd be none the wiser. The area cost of such an additional CPU would be essentially undetectable, less than 0.01mm2 on a modern process.

Unless you're talking about making your ASIC, but in that case, a commercial offering (which typically comes with a source code license) gives you just as much access to review the code for hidden firmware.

This gets repeated over and over but I don't get it. You could build a blob-free ARM chip. Existing RISC-V chips already have/had blobs. Freeeeedom is orthogonal to the ISA.

This has basically nothing to do with the ISA. It's not the ISA that hides secrets and requires binary blobs. A chip is much more than an instruction set, hence why dealing with the proprietary undocumented garbage to bring up a new ARM SoC is a pain in the ass even if you've memorized every ARM instruction down to its encoding...

If RISC-V gets picked up and used by mainstream chipmakers in the SBC & TV BOX & mobile space, there is no doubt we will end up with chips that have proprietary undocumented garbage interfaces. Just like they also now take something like the (open source) ATF or OP-TEE, implement support for their own chip, and then publish a binary blob without source code.