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0 pointsmicrocolonel7y ago0 comments

> AArch64 uses adrp in almost exactly the same way that RISC-V uses auipc to access literal pools.

I meant that you could forego the constant pool (ARM calls them literal pools?) for branch targets in some use cases due to the added range of RISC-V U immediates, and in more cases than you can with ARMv8 (which only now offers 16-bit immediates in some cases, AFAIK [ARM's infocenter timed out, and I couldn't find it in the manual with search, so I'm basing this on some forum post by some dude]). With auipc you can compute an address 1GiB two ways from the pc, to the byte, and with no base register to be set in your JIT entry frames and allocated around.

In the V8 "arm64" port, it seems they manage 128MB as a practical matter:

https://github.com/v8/v8/blob/master/src/arm64/constants-arm...

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brandmeyer7y ago

For the most part, ARMv8 immediates are 12 bits for [base + displacement] addressing. However, most of the modes also allow you to use natural scaling of the displacement (or index in [base + index] modes). So you can reach the 4096th byte, or the 4096th pointer in a struct (and other sizes in between).

That 128 MB limit is interesting. Its the limit for direct pc-relative calls in ARMv8 without resorting to adrp.

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