Granted, the hardware is somewhat limited for now, since it's only in-order.
A development board is light years away from a 19” rack mountable server with out-of-band management (lights out management) and everything else that goes into such a design. You know, the kind of hardware that is actually usable in production and not just a cool toy that might or might not spawn production systems some day. I for one am not content to just tinker with toys; I want servers so I can get some real work done.
The biggest differences are immediate arithmetic and load/store offsets are 12 bit on RISC-V vs 16-bit on MIPS. To compensate, LUI loads 20 bits on RISC-V vs 16 bits on MIPS. So it's only immediates or offsets between +/-2K and +/-32K that are different.
Also RISC-V does compare two registers for ordering and branch in one instruction, which older MIPS can't do.
How arbitrary is arbitrary? ARMv7's Thumb2 format immediates are composed of a 8-bit field shifted by up to 5 bits. So you can form any 32-bit variable, but with limited precision.
ARMv8 modified immediates can describe a contiguous run of ones followed by a contiguous run of zeros, and SWAR variations of the same. So you can describe things like a repeating 0x3f... for example.
Do either of those formats encompass the kinds of literals that you need in the V8 JIT?
> so you can use pc-relative addressing ... at a penalty of one word
Since the RISC-V PC-relative addressing capabilities are similar to ARMv8 (adrp) and x86-64 (rip-relative addressing), I would have though that this is basically a non-problem. You pay one more live register to hold the page address, but you also get more registers, so I would think it mostly washes out. Where do you pay a penalty?
edited to add: here's HN's discussion at the time: https://news.ycombinator.com/item?id=17489504
