A survey of attacks against Intel x86 over last 10 years (2015) [pdf] (opens in new tab)

No they really cannot. Many of the optimizations CPU do on the fly are akin to JIT recompilers. (in microcode and schedule side) These cannot be effectively done ahead of time yet, at least not without an instruction accurate profiling.

Not to mention VLIW wastes CPU instruction cache for instructions that aren't ran.

It is no accident that CPUs and compilers gravitated towards RISC.

>Microsoft has been working on a VLIW too (yes I know, not exactly VLIW, it's close enough).

VLIW isn't going anywhere. Generating code for VLIW isn't getting any easier anytime soon, and the complexity doesn't help the formal proofing that's become a must thanks to data protection requirements of the current world.

If we've learned anything in the past decades, it'd be that RISC is the only valid approach going forward.

Mill is awesome. I'm afraid it has too many revolutionary ideas in one package, though, which could impede its widespread adoption.

> separate hypervisor mode

RISC-V, without the hypervisor extension, meets the requirements for Popek-Goldberg virtualization, unlike x86. The problem is that classic virtualization requires shadow paging for memory virtualization, which can be slow. The hypervisor extension (not yet finalized) only adds two level nested paging, a few shadow CSRs, and IIRC a few more interrupt handling registers. The hypervisor extension itself is virtualizable (again, with shadow page tables).

Is there a different ISA that you would have preferred to see as the basis for an open hardware industry?

Please don't spread misinformation. RISC-V has a well-thought out machine layer which is open source in all existing implementations[1]. You can easily modify the M layer if it's interfering with the performance or security of your OS.

The virtualization extension hasn't been finalized (but they are working with key KVM people), but it will perform a lot better than a theoretically pure self-virtualizable ISA.

[1] https://github.com/riscv/riscv-pk

RISC-V is simpler, and easier to implement. Instruction density is very good with the compressed extension, and is applicable to many niches, from in-order low power embedded cores, to high performance out of order desktop CPUs. We can expect marginal improvements over x86 and ARM across the board.

On the other hand, it is not finished. A number of extensions have yet to be frozen, and we're just beginning to see commercial processors (I mean, where the ISA is exposed to the end user. NVIDIA already uses RISC-V internally).

I believe you have to pay royalties for Arm while RISC-V is completely open source.

I don't know enough to say if this is accurate or not. However there are working groups reviewing the memory model[1] (also implementing fast ISRs[2]) so if there are performance problems in this area then they're being looked at.

[1] https://content.riscv.org/wp-content/uploads/2018/05/14.25-1... https://content.riscv.org/wp-content/uploads/2018/05/10.40-1...

[2] https://content.riscv.org/wp-content/uploads/2018/05/08.45-0...