This is a deep rabbit hole because modern processors are speculatively executing THOUSANDS of instructions ahead. So what you have/haven't written to memory is slightly existential.
Here is a good blog post about it http://preshing.com/20120930/weak-vs-strong-memory-models/
The TLDR: x64 tries REALLY HARD to ensure your pointers always have the newest data. ARMv6, very much. ARMv7 kind of. ARMv8 fairly.
With up to 96 in scheduler. 72 loads, and 56 writes.
Link: (summery you find hard intel references internally) https://en.wikichip.org/wiki/intel/microarchitectures/skylak...
224 per core. We're talking concurrency. So a 10core, 20HT server class can have 2240 instructions in flight.
> http://preshing.com/20120930/weak-vs-strong-memory-models/
If you want more details of memory models of some CPU architectures, read
> http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2...
Note that "x86 OOStore" is not a model that you should be concerned about (according to https://groups.google.com/forum/#!topic/linux.kernel/2dBrSeI... it was only used on IDT WinChip)
For a perspective on memory barriers for different memory models with a focus on the Linux kernel look at
> https://www.kernel.org/doc/Documentation/memory-barriers.txt
If you are specifically interested in some subtile details of the x86 memory model, have a look at
> http://www.cl.cam.ac.uk/~pes20/weakmemory/index3.html
Best begin with
> http://www.cl.cam.ac.uk/~pes20/weakmemory/cacm.pdf
---
I hope this should give you enough information to start reading up on the subject.
The 2nd part of his talk goes into some of the differences between x86 and other architectures (about 31 min in):
https://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-20...
See: https://en.wikipedia.org/wiki/Memory_ordering#In_symmetric_m...
